International Business Machines Corporation

Samsung Electronics Co., Ltd.

Elpis Technologies Inc.

Shawn Peter Fetterolf

Kangguo Cheng

Ahmet Serkan Ozcan

Adam J McPadden

Lawrence Alfred Clevenger

Terence B Hook

Donald Francis Canaperi

Michael A Guillorn

Stephen Peter Ayotte

Daniel A Corliss

Timothy M Sullivan

Derren Neylon Dunn

Brent A Anderson

Chi-Chun Liu

Theodoros Anemikos

Nicolas Degors

Ali Khakifirooz

Christian Lavoie

Arvind Kumar

Roger Allan Quon

Jin-Ping Han

Paul Stephen McLaughlin

Terry Hook

3D nanochannel interleaved devices for molecular manipulation are provided. In one aspect, a method of forming a device includes: forming a pattern on a substrate of alternating mandrels and spacers alongside the mandrels; selectively removing the mandrels from a front portion of the pattern forming gaps between the spacers; selectively removing the spacers from a back portion of the pattern forming gaps between the mandrels; filling i) the gaps between the spacers with a conductor to form first electrodes and ii) the gaps between the mandrels with the conductor to form second electrodes; and etching the mandrels and the spacers in a central portion of the pattern to form a channel (e.g., a nanochannel) between the first electrodes and the second electrodes, wherein the first electrodes and the second electrodes are offset from one another across the channel, i.e., interleaved. A device formed by the method is also provided.

3D nanochannel interleaved devices

A method of manipulating a molecule having a dipole moment is provided. A non-limiting example of the method includes providing an array of electrodes with each respective electrode in electrical communication with a respective interconnect. Each respective electrode is individually addressable through its respective interconnect, and each respective electrode is capable of generating an electromagnetic field when stimulated. The method provides the molecule above the array of electrodes and stimulates one or more electrodes within the array of electrodes to manipulate the molecule.

Manipulation of a molecule using dipole moments

Provided are techniques for generating fully depleted silicon on insulator (SOI) transistor with a ferroelectric layer. The techniques include forming a first multi-layer wafer comprising a semiconductor layer and a buried oxide layer, wherein the semiconductor layer is formed over the buried oxide layer. The techniques also including forming a second multi-layer wafer comprising the ferroelectric layer, and bonding the first multi-layer wafer to the second multi-layer wafer, wherein the bonding comprises a coupling between the buried oxide layer and the second multi-layer wafer.

Fully depleted SOI transistor with a buried ferroelectric layer in back-gate

An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

Electrical mask validation

Techniques regarding self-sterilizing touch sensors are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a heating element. Also, the apparatus can comprise a protective layer adjacent to the heating element. The heating element can generate heat based on a pressure applied to the protective layer and can sterilize the protective layer.

Self-sterilizing sensor

Crossbar arrays (e.g., Resistive Processing Unit (RPU) accelerators) are leveraged to create a Physically Unclonable Function (PUF) that exploits variations, such as statistical process variation in manufacture or operation, to generate key material to secure information in a computing environment. One environment is a cloud compute infrastructure whose shared resources are used to process workloads. During RPU accelerator use, the state of the RPU's bits are changed by reproducible inputs, e.g., stochastic pulses applied to change resistive values in the array, and the corresponding changes in the RPU array state captured. These responses, which cannot be reproduced from another device due to random device variations across chips that embody the RPUs, are then used to generate (or facilitate generation of) the cryptographic material. In one embodiment, inputs applied to the RPU accelerator array are generated from a pseudo-random number generator that is otherwise associated with the RPU accelerator.

Generating key material for information security using a resistive processing unit (RPU) accelerator array as a physically unclonable function (PUF)

According to embodiments of the present invention, a semiconductor device includes a first transistor located on a first fixed charge dielectric layer and a second transistor located on a second fixed charge dielectric layer. The first fixed charge dielectric layer and the second fixed charge dielectric layer are differently charged such that the first transistor and the second transistor have different threshold voltages.

Fully depleted semiconductor-on-insulator transistors with different buried dielectric layer charges and different threshold voltages

A contactless readable programmable transponder to monitor chip join and method of use are disclosed. The method includes reading a frequency of an oscillator associated with a chip module. The method further includes correlating the frequency with a bond quality of the chip module.

Contactless readable programmable transponder to monitor chip join

A semiconductor structure is provided. A non-limiting example of the structure includes a substrate and a plurality of first pillars of a conductive material above a first portion of the substrate. The structure further includes a plurality of second pillars of the conductive material above a second portion of the substrate, wherein the plurality of first pillars are offset by a gap distance from the plurality of second pillars along a longitudinal axis.

Interleaved structure for molecular manipulation

Embodiments are directed to a method of providing access verification for a system that includes activating a security control device, which is in communications with a host device. The method also includes having the security control device receiving a verification signal coming from outside the system while being locally-based, and comparing the verification signal to a table of stored criteria values. The device then chooses a response based on that comparison and sends an access determination signal based on the response.

User access verification

A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected to the first VFET, and including a second fin and a second gate formed on the second fin, and a third VFET formed on the substrate and including a third fin, the first gate being formed on the third fin.

Semiconductor device and method of forming the semiconductor device

Various methods and structures for fabricating a semiconductor chip structure comprising a chip identification 'fingerprint' layer. A semiconductor chip structure includes a substrate and a chip identification layer disposed on the substrate, the chip identification layer comprising random patterns of electrically conductive material in trenches formed in a semiconductor layer. The chip identification layer is sandwiched between two layers of electrodes that have a crossbar structure. A first crossbar in the crossbar structure is located on a first side of the chip identification layer and includes a first set of electrical contacts in a first grid pattern contacting the first side of the chip identification layer. A second crossbar in the crossbar structure is located on a second side of the chip identification layer and includes a second set of electrical contacts in a second grid pattern contacting the second side of the chip identification layer.

Chip security fingerprint

An embodiment of the invention may include a semiconductor structure for ensuring semiconductor design integrity. The semiconductor structure may include an electrical circuit necessary for the operation of the semiconductor circuit and white space having no electrical circuit. The semiconductor structure may include an optical pattern used for validating the semiconductor circuit design formed in the white space of the electrical circuit. In an embodiment of the invention, the optical pattern may include one or more deposition layers. In an embodiment of the invention, the optical pattern may include covershapes. In an embodiment of the invention, the optical pattern may be physically isolated from the electrical circuit. The optical pattern may include a Moir&#xe9; pattern.

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Cornwall, VT, United States of America

Shawn Peter Fetterolf