Realtek Semiconductor Inc.

Shawn Min

Yi-Chun Hsieh

Hsi-En Liu

Chun-Ta Ho

Tsung-Ming Chen

Jen-Huan Tsai

Ming-Hui Tung

Po-Chiun Huang

Cheng-Yu Liu

Chun-I Kuo

Yi-Jang Wu

Yu-Ting Chung

You-Jyun Peng

Chieh-Yuan Hsu

An amplifier includes an amplifier circuit and a gain adjusting circuit. The amplifier circuit has a design gain and a real gain and is configured to output an output signal according to an input signal and the real gain. The gain adjusting circuit is coupled to the amplifier circuit and is configured to receive the input signal to compare a voltage of the input signal with a first reference voltage, wherein when the voltage of the input signal exceeds the first reference voltage, the gain adjusting circuit increases the real gain of the amplifier circuit, so that the real gain approach the design gain.

Amplifier

The present disclosure discloses a sample and hold amplifier circuit that includes a positive and a negative terminal capacitor arrays, a positive and a negative terminal switch arrays and a differential output circuit. A second terminal of each of bit capacitors in the positive and the negative terminal capacitor arrays are respectively coupled to a positive and a negative output terminal. In a sampling time period, according to a first connection relation, each of the connected bit capacitors is controlled to receive a polarity input voltage to perform a gain modification. In a holding time period, according to a second connection relation, each of the connected bit capacitors is controlled to receive an offset modification voltage to perform an offset modification. A positive and a negative output voltages are generated at the positive and the negative output terminal to be outputted as a pair of differential output signals by the differential output circuit.

Sample and hold amplifier circuit

The present invention discloses a bias current generation circuit. An operation amplifier compares an input voltage having a zero-temperature coefficient and a feedback voltage to generate a driving voltage. An output transistor generates a bias current according to the driving voltage. A variable resistive circuit is electrically coupled to the output transistor through a feedback node to generate the feedback voltage according to the bias current and includes series-coupled resistors and switch transistors. Each of the resistors has a resistance having a positive temperature coefficient and includes a current input terminal and a current output terminal. Each of the switch transistors is electrically coupled between the current output terminal of one of the resistors and a ground terminal. One of the switch transistors turns on according to a control voltage variable according to the temperature variation to enable resistors to generate the resistance having a negative temperature coefficient.

Bias current generation circuit

Disclosed is an open loop fractional frequency divider including an integer divider, a control circuit, and a phase interpolator. The integer divider processes an input clock according to the setting of a target frequency to generate a first frequency-divided clock and a second frequency-divided clock. The control circuit generates a coarse-tune control signal and a fine-tune control signal according to the setting. The phase interpolator generates an output clock according to the first frequency-divided clock, the second frequency-divided clock, and the two control signals. The two control signals are used for determining a first current, and their reversed signals are used for determining a second current. The phase interpolator controls a contribution of the first (second) frequency-divided clock to the generation of the output clock according to the first (second) frequency-divided clock, the reversed signal of the first (second) frequency-divided clock, and the first (second) current.

Open loop fractional frequency divider

An amplifier circuit is provided, which includes an input stage circuit, at least one impedance component and a current supply circuit, where the input stage circuit is coupled between at least one input terminal of the amplifier circuit and at least one output terminal of the amplifier circuit, the impedance component is coupled between a first reference voltage and the output terminal, and the current supply circuit is coupled between a second reference voltage and the output terminal. The input stage circuit is arranged to generate a signal current in response to an input signal on the input terminal, and the current supply circuit is arranged to provide at least one adjustment current. In addition, a common mode voltage level of an output signal on the output terminal is controlled by the adjustment current, to allow the amplifier circuit to perform low voltage operations.

Amplifier circuit

The present invention provides a clock generating circuit, wherein the clock generating circuit includes a phase detector, an integral path, a proportional path, a bias path and an oscillator. In the operations of the clock generating circuit, the phase detector generates a detection result according to a reference signal and a feedback signal, a first charge pump within the integral path generates a first control signal according to the detection result, a second charge pump within proportional path generates a second control signal according to the detection result, a low-pass filter within the bias path filters the first control signal to generate a third control signal, and the oscillator generates a clock signal according to the first control signal, the second control signal and the third control signal.

Clock signal generating circuit and method for generating clock signal

The present invention provides a decision feedback equalizer including a first path and a second path. The first path includes a first sampling circuit and a first latch circuit, wherein the first sampling circuit generates a first set signal and a first reset signal according to an input signal, a second set signal and a second reset signal, and the first latch circuit generates a first digital signal according to the first set signal and the first reset signal. The second path includes a second sampling circuit and a second latch circuit, wherein the second sampling circuit generates the second set signal and the second reset signal according to the input signal, the first set signal and the first reset signal, and the second latch circuit generates a second digital signal according to the second set signal and the second reset signal.

Decision feedback equalizer

The present invention discloses a differential signal skew detecting circuit configured to detect a skew of a differential signal. An embodiment of the circuit includes: a common mode voltage outputting circuit configured to output a common mode reference voltage and a common mode skew voltage; and a skew detecting circuit configured to inspect the common mode reference voltage and the common mode skew voltage according to a clock signal so as to output a skew detection value, in which when the skew detecting circuit detects the skew of the differential signal, the skew detection value is a first value, and when the skew detecting circuit detects no skew of the differential signal, the skew detection value is a second value.

Circuit and method for differential signal skew detection

A circuit for generating a horizontal synchronizing signal of a display includes: a first comparator which is used to compare a luminance signal of a Component Video Connector of the display and a first reference signal to generate a compared signal; a control circuit which is used to generate a first digital controlled signal according to the compared signal; a first digital-to-analog converter which is used to generate the first reference signal according to the first digital controlled signal; a second digital-to-analog converter which is used to generate a second reference signal according to a second digital controlled signal generated by the control circuit, wherein the second digital controlled signal is determined by the first digital controlled signal; and a second comparator which is used to compare the luminance signal and the second reference signal to generate the horizontal synchronizing signal.

Circuit for generating horizontal synchronizing signal of display and associated method

A successive approximation (SAR) analog-to-digital converter for generating a digital signal of N bits is provided. The converter includes a capacitive digital-to-analog conversion circuit including an (N&#x2212;1)-th conversion unit to a first conversion unit. Each of the first conversion unit to the (N&#x2212;2)-th conversion unit includes a capacitor. The (N&#x2212;1)-th conversion unit comprises a number of sub-capacitors. Each of the sub-capacitors of the (N&#x2212;1)-th conversion unit has substantially the same capacitance with corresponding capacitor of the first conversion unit to the (N&#x2212;2)-th conversion unit. During the conversion process, the SAR control circuit, after generating the value of the most significant bit (MSB) of the digital signal, generates the value of the next bit by controlling the (N&#x2212;1)-th conversion unit. Then, the SAR control circuit repeatedly uses at least one of the sub-capacitors of the (N&#x2212;1)-th conversion unit to generate the value of other bits to perform self linear compensation.

Successive approximation analog to digital converter and method thereof

Disclosed are an analog-to-digital converting apparatus, an analog-to-digital converting method and a touch control apparatus adapted to convert a divided voltage generated according to a power voltage and a ground voltage. The analog-to-digital converting apparatus includes a first sample-and-hold circuit for sampling and holding the divided voltage, a second sample-and-hold circuit for sampling and holding the power voltage, and an analog-to-digital converter coupled to the first and second sample-and-hold circuits. The analog-to-digital converter converts the divided voltage from the first sample-and-hold circuit to a digital value according to the power voltage held by the second sample-and-hold circuit and the ground voltage. The first and second sample-and-hold circuits sample the divided voltage and the power voltage before the analog-to-digital converter converts the divided voltage, and hold the sampled divided voltage and the sampled power voltage at least during conversion of the divided voltage by the analog-to-digital converter.

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Hsinchu County, Taiwan

Shawn Min