Agere Systems Inc.

Lsi Corporation

At&t Bell Laboratories

At+t Corp.

American Telephone & Telegraph Co., At&t Bell Laboratories

American Telephone and Telegraph, Co.

Shawn Michael Logan

David M Embree

Pervez Mirza Aziz

Adam Benjamin Healey

Lane Allen Smith

Vladimir Sindalovsky

Christopher John Abel

Xingdong Dai

Joseph Anidjar

Yasser Ahmed

HaoQiong Chen

Ellis E Nease

Shujiang Wang

Chunbing Guo

An electronic device package includes first and second electrodes of a package substrate. The first electrode has fingers formed from a first metal level and is configured to operate at a first DC potential. The second electrode has fingers formed from the first metal level interdigitated with the fingers of the first electrode. A via conductively connects the second electrode to a second metal level. The second metal level is configured to operate at a second DC potential. The first and second DC potentials are thereby capacitively coupled through the interdigitated electrodes.

Decoupling capacitor

In described embodiments, a receiver includes a clock and data recovery (CDR) module with a voltage control oscillator (VCO) and a Sigma-Delta modulator in an integral loop control of the VCO. Providing finer resolution by the Sigma-Delta modulator reduces quantization noise in the integral control loop when compared to a loop without a Sigma-Delta modulator in the integral loop. Sigma-Delta modulation within the integral loop control of a VCO-based CDR reduces effective quantization of the VCO integral word control, allowing the proportional loop control compensation to i) reduce effective quantization of the VCO integral word control and, ii) enhance receiver jitter tolerance in presence of periodic-jitter, serial data whose frequency is offset from the nominal rate and serial data whose nominal frequency is modulated by a spread spectrum clock.

CDR with sigma-delta noise-shaped control

A method for reducing noise in an output of a voltage regulator at frequencies above a closed loop bandwidth, by providing a noise injection path for injecting external noise into the voltage regulator, where the noise injection path becomes active at the frequencies above the closed loop bandwidth, where the noise injection path reduces the noise in the output of the voltage regulator.

Power supply noise injection

Described embodiments provide a method and system for signal compensation in a SERDES communication system that includes monitoring the quality of a data signal after passing through a transmission channel. The quality of the data signal is monitored with at least one of a BER calculation algorithm and a received eye quality monitoring algorithm. Variations in channel length of the transmission channel are compensated for by i) adjusting a length of transmission line delay of the data signal from the transmission channel, ii) comparing the data signal quality with a threshold for the adjusted data signal; and iii) repeating i) and ii) until the data signal quality meets the threshold.

Compensation for transmission line length variation in a SERDES system

Compensating transmission line to reduce sensitivity of performance due to channel length variation

Methods and apparatus are provided for compensating for skew in a differential signal using non-complementary inverters. A skew attenuator is provided for a differential signal having a P rail and an N rail. The skew attenuator comprises one or more non-complementary inverters for compensating for skew between the P rail and the N rail. The non-complementary inverters attenuate a time difference of arrival of transitions for the P rail and the N rail. An exemplary skew attenuator includes a first non-complementary inverter associated with each of the P rail and the N rail. The P rail and the N rail signals are each applied to a gate of one of the first non-complementary inverters, and drains of the first non-complementary inverters provide differential output signals OUTP and OUTN. The exemplary skew attenuator also includes an additional non-complementary inverter associated with each of the first non-complementary inverters.

Methods and apparatus for compensating for skew in a differential signal using non-complementary inverters

Methods and apparatus are provided for calibrating a voltage controlled oscillator, such as an N-stage voltage controlled ring oscillator. The voltage controlled oscillator comprises a power supply input and at least one gate delay element and has a frequency that is a function of a delay of the gate delay element and a voltage applied to the power supply input. A voltage controlled oscillator is calibrated by varying an output voltage of a programmable voltage source through a range of values; applying the output voltage to the power supply input of the voltage controlled oscillator; comparing an output clock frequency of the voltage controlled oscillator to a reference frequency clock for each of the output voltage values; and selecting a value of the output voltage that provides an approximate minimum frequency difference between the output clock frequency and the reference frequency clock.

Method and apparatus for calibrating a voltage controlled oscillator by varying voltage applied to power supply input

The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process.

Programmable linear trimming method and system for phase locked loop circuit calibration

A segmented inductor for use with a tuning circuit, a method of increasing a self-resonant frequency of a tuning circuit and an oscillator employing the circuit and method. In one embodiment, the tuning circuit includes a first inductive element having a first intrinsic shunt capacitance. The tuning circuit also includes a second inductive element, coupled in series with the first inductive element, having a second intrinsic shunt capacitance. The first and second inductive elements cooperate to reduce a total shunt capacitance associated therewith thereby increasing a self-resonant frequency of the tuning circuit.

System and method of increasing a self-resonant frequency of a tuning circuit and an oscillator employing the same

Oscillation is easily and reliably initiated in an oscillator by increasing the gain of the circuit at startup time. For example, the gain of an oscillator circuit may be increased at startup by reducing the value of a user controlled impedance until oscillation commences. Alternatively, or in combination, the input impedance of an amplifier used in the oscillator may be reduced at startup to facilitate the initiation of oscillation.

Oscillator with increased reliability start up

An undesirable relationship between user applied input frequency control voltage and output frequency of a voltage controlled oscillator is counteracted by controlling the characteristics of an amplifier stage in the oscillator as a function of frequency control signal in addition to controlling the output frequency of the oscillator as a function of the capacitance of a user controlled variable capacitance in response to the frequency control signal.

Voltage controlled oscillator with improved voltage versus frequency

A voltage variable capacitor (VVC) having two terminals in a variable frequency crystal oscillator integrated into a common substrate with the oscillator circuitry and isolated therefrom. The VVC is constructed using the same processing steps as the oscillator circuitry and achieves low series resistance and wide capacitance variation by utilizing a substrate or epitaxial layer (body) having a well with a diffused region therein. The region, of the same conductivity type as the well and a first one of the two terminals, forms a rectangular ring in the well. Over the region and insulated therefrom, a conductive layer is deposited to provide a second one of the two terminals. Both terminals are electrically isolated from the body.

Voltage controlled variable capacitor and oscillator using it

Maximum frequency range in a VLSI voltage controllable crystal oscillator is obtained with a two-stage amplifier with feedback across both stages. The first stage is implemented by an MOS transistor connected in source-follower configuration to minimize input capacitance, and the second stage is implemented by a bipolar transistor to provide the needed gain. A bidirectional voltage limiter connected to a crystal node limits the oscillations to a symmetrical waveform. The bias of an output buffer amplifier may be selectively shifted to maintain optimum duty cycle with the different triggering levels of diverse logic driven by the oscillator, and the bias may be dynamically driven by an analog signal to provide a duty cycle-modulated output.

High frequency VLSI oscillator

Maximum frequency range in a CMOS voltage-controllable crystal oscillator is obtained with a two-stage amplifier with feedback across both stages. The first stage is connected in source-follower configuration to minimize input capacitance, and the second stage provides the needed gain. To eliminate body effect, the source electrode and body of the second stage CMOS device are connected together. A bidirectional voltage limiter connected to a crystal node limits the oscillations to a symmetrical waveform. Changes in effective duty cycle caused by the different triggering levels of diverse logic connected to the oscillator output are compensated for by selectively shifting dc bias to a buffer amplifier.

High frequency CMOS oscillator

A track and hold circuit comprising an electronic switch and a signal storing device. During a tracking interval, the switch couples a varying input signal from an input node to the storing device in response to at least one track control signal. In a holding interval, the switch isolates the input node in response to at least one hold control signal. An input-signal-independent and substantially constant track-to-hold offset is provided by the use of selected track and hold control signals. Specifically, the track and hold control signals respectively vary with input signal during each tracking and each holding interval and have a substantially constant difference therebetween. In the disclosed embodiments, the track and hold circuit can be easily modified to reduce the effects of feedthrough and droop.

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Andover, MA, United States of America

Shawn Michael Logan