International Business Machines Corporation

Shawn Michael Lambeth

Charles Scott Graham

Paul Edward Movall

Daniel Frank Moertl

Thomas R Sand

Gregory Michael Nordstrom

Timothy Roy Block

Lee Anton Sendelbach

Chetan Mehta

Ellen Marie Bauman

Travis James Pizel

Gene Steven Van Grinsven

Stephanie Maria Forsman

William Joseph Armstrong, Jr

Lee Patrick Prissel

Paul John Johnsen

William D Tarara

Jason Alan Clegg

Timothy Jerry Schimke

An address translation manager creates a set of chained tables that may be allocated in non-contiguous physical memory, and that may be dynamically resized as needed. The chained tables comprise one or more tables that each correspond to a logical partition, with each table including a pointer to a table corresponding to a virtual connection in the logical partition. The chained tables are managed by the address translation manager, which uses the system memory manager to dynamically allocate and free memory for a chained table as needed.

Address translation manager and method for a logically partitioned computer system

A method, apparatus, system, and signal-bearing medium that in an embodiment dynamically allocate and/or deallocate data structures on demand to respective partitions in a logically-partitioned electronic device. The data structures are associated with an adapter, and the partitions may use the data structures to access the adapter and, in an embodiment, to send and/or receive messages across a network.

On-demand allocation of data structures to partitions

An apparatus and method for recording segment execution times in a processing system are provided. The method includes the steps of recording a timestamp corresponding to the beginning of a segment to be executed, wherein the recording step is conducted through a firmware operation. The method further includes the step of updating the timestamp with an elapsed segment execution time, wherein the updating step is conducted through a plurality of hardware based operations that are executed without firmware interaction.

Apparatus and method for adaptive address-based historical utilization recording

A method and an apparatus is presented for updating flash memory that contains a write protected code, a first copy of rewritable recovery code, a second copy of rewritable recovery code, and a rewritable composite code. Each block of rewritable code contains a checksum code to detect if the block of code has been corrupted. If it is detected that the first copy of the recovery code is corrupted then the second copy of the recovery code is copied into the first copy of the recovery code. If it is detected the second copy of the recovery code is corrupted then the first copy of the recovery code is copied into the second copy of the recovery code. The recovery code is responsible for checking and updating the composite code. If it is detected the composite code is corrupted then a fresh copy of the composite code is obtained from a removable storage device or a network connection. The data processing system is booted by executing the write protected code, the first copy of the recovery code, and the composite code. There is a minimum of redundant code by only replicating two copies of the recovery code while, at the same time, guaranteeing both the integrity and the updateability of the flash memory.

Method and apparatus for updateable flash memory design and recovery with minimal redundancy

A primary PCI bus and multiple secondary PCI busses of a PCI expansion card interface, are interconnected by a routing circuit. The routing circuit functions as a switched bridge between the primary PCI bus and each of the secondary PCI busses, respectively, by associating each secondary PCI bus with an address range, and forwarding a command received from the primary PCI bus to a secondary PCI bus mapped to an address range including the address of the command. Furthermore, the routing circuit forwards commands intended for the primary PCI bus from the secondary PCI busses. In addition, the routing circuit directly routes commands between the secondary PCI busses, when commands received from one secondary PCI bus are intended for another PCI bus, without use of the primary bus. As a result, traffic and latency on the primary PCI bus is reduced and efficiency is increased.

Apparatus and method of PCI routing in a bridge configuration

An input/output bus architecture that includes: an input/output bus; an input/output device connected to the input/output bus; a main processor, connected to the input/output bus, for executing a device driver corresponding to the input/output device, the device driver generating load/store commands for the input/output device; and a load/store assist engine, connected to the input/output bus and yet independent of the main processor, for loading/storing data to/from the input/output device according to the load/store commands from the device driver. The load/store assist engine decouples the main processor from latencies associated with execution of the load/store commands. The device driver is reassigned to the main processor, rather than being found in a device that is external to the main processor, such as an input/output processor.

Load/store assist engine

A method, device and system for configuring multifunction I/O device adapters connected to a bus utilizes a slot owner configuration register to identify the ownership of each function slot within the multi-function I/O device adapter. An intelligent I/O device adapter or controller within the multi-function I/O device adapter may control other I/O adapters located in other function slots through the information provided in the slot owner configuration register. Ownership of each slot is initially set, upon power up, to the host unit or processor complex. Thereafter, each intelligent I/O device adapter or controller determines the presence of adapters at other function slots to be controlled, and records this information in the slot owner configuration register.

Method and system for remote function control and delegation within

An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O completion events together with a single processor interrupt in a manner that balances I/O operation latency requirements with processor utilization requirements to optimize overall computer system performance. The invention sends a message from a processor complex to an I/O adapter on an I/O bus commanding an I/O device connected to the I/O adapter to perform a function. Upon completion of the commanded function, the message processor in the I/O adapter generates a message and sends it to the processor complex on the I/O bus. The message is enqueued in the message queue of the memory, a message count is updated, and processor complex interrupt is signalled if and when the message count exceeds a message pacing count. A signalling timer may also be programmed with a fast response time value if the message has a relatively high latency or with a slow response time value if the message has a relatively low latency. The signalling timer is started when the message is enqueued and the processor complex interrupt is then signalled when the message count exceeds the message pacing count or when the signalling timer has elapsed.

Interrupt and message batching apparatus and method

An apparatus, system and method permitting a variety of reset procedures and corresponding reset states. A device reset control register is provided for each I/O device adapter in single function or multifunction devices. The device reset control registers permit a greater degree of control over single function devices, multifunction device as a whole and individual device functions within a multifunction device. A device immediate status register synchronizes the various reset procedures. A logical power on reset procedure, a directed unit reset procedure and a directed interface reset procedure utilize the greater degree of control that the device reset control registers provide to force the I/O device adapter, single function device or multifunction device into a corresponding logical power on reset state, a directed unit reset state or a directed interface reset state. Each of these reset states is well-defined and has the advantage of predictable behavior during and after execution of the corresponding reset procedure. A built-in self-test procedure is also defined that sequentially examines each function associated within a multifunction device connected to the local bus to coordinate the initiation, execution and completion of built in self-tests.

Enhanced reset and built-in self-test mechanisms for single function and

An apparatus, system and method permitting dynamic configuration of I/O device adapters connected to a bus utilizes a function configuration register to store a READY/NOT READY status for each of the I/O device adapters. Upon the occurrence of a reset condition, dynamic configuration decision logic detects which I/O device adapters are connected to the bus, determines configuration parameters for each connected I/O device adapter, initializes the configuration space for each connected I/O device adapter, and then sets a corresponding flag in the function configuration register to indicate ready status. An I/O device driver interrupts a configuration process to examine the function configuration register. If ready status can be confirmed from this function configuration register within a time out period, then the configuration process may proceed; otherwise, a device error recovery process is initiated.

System for dynamically configuring I/O device adapters where a function

An I/O system including a processor complex and system main memory connected to I/O adapters via I/O adapters and I/O bus. A message transport mechanism and method stores an upstream message queue and a downstream message queue in system main memory. Queue addresses are stored both in system main memory and designated registers of I/O adapters. The I/O adapters utilize the queue addresses to manage the transfer of downstream command messages and to send upstream response messages to the system main memory via direct memory access across the I/O bus.

Message transport mechanisms and methods

A computer system has a system memory, a central processing unit, an input/output controller, and at least one device. When the central processing unit wants data transferred to/from system memory from/to the device, it sends Indirect DAta Address Word (IDAW) commands to the I/O controller. Instead of performing a direct memory access (DMA) operation for each IDAW command, the I/O controller starts an IDAW look ahead procedure. In this procedure, the I/O controller checks to see if the system addresses of the system memory specified in the IDAW commands are contiguous. If so, the procedure combines IDAWs that specify contiguous system addresses up to the maximum DMA transfer length. Using this procedure, the number of DMA operations sent to the system memory is minimized, and the computer system has more efficient data transfer operations.

Growing community of inventors

Pine Island, MN, United States of America

Shawn Michael Lambeth