Cortina Systems Corporation

Inphi Corporation

Shawn Lawrence Scouten

Malcolm Stevens

Ryan Patrick Donohue

Fredrik Olsson

Brian Wall

Kenji Suzuki

Kevin Parker

Colin Cramm

Stephane Dallaire

Med Belhadj

Jeff P Kirsten

Apparatus and techniques relating to data interface power consumption control are disclosed. Components of a data transfer module may be selectively moved between their normal operating states and reduced power states at times when the data transfer module is not to be used for transferring data. Decisions as to particular components that are to be moved to their reduced power states may be based on respective timing characteristics of the components and/or respective power consumption characteristics of the components, for example. In some embodiments, an action may be performed to reduce a powering up time of the data transfer module when normal operation of the data transfer module is to resume. In the case of a multiple-connection interface having respective data transfer modules for each connection, the interface may be partially shut down by moving a subset of the data transfer modules into reduced power states.

Data interface power consumption control

An AC coupling circuit is provided that has a level shifter circuit having a p input voltage and an n input voltage and producing a p output voltage and a p output voltage. There is a common mode voltage adjustment feedback circuit configured to cause a common mode voltage output to tend towards a specified reference voltage, the common mode voltage output being an average of the p output and n output voltages of the level shifter circuit. In combination, the level shifter circuit and the feedback circuit allow the interconnection of a first circuit that operates at a first, unspecified, common mode voltage to be connected to a second circuit having a required common mode voltage. The level shifter may be formed of adjustable components such that the frequency response of the level shifter circuit can be adjusted to compensate for a frequency response of an interconnect between the first circuit and the second circuit.

System and method for AC coupling

Integrated jitter compliant clock signal generation apparatus and methods are provided. Input signals having different frequencies are used to generate respective clock signals having closely spaced frequencies. The input signals might be generated, for example, in adjacent Phase Locked Loops (PLLs) which receive reference clock signals. The reference clock signals, or signals from which the reference clock signals originate, are also closely spaced. The closely spaced reference clock signals are effectively separated for cleanup and then brought back together to provide the closely spaced clock signals. This allows cleanup of the closely spaced reference clock signals to occur at staggered and more widely spaced frequencies. These techniques could also be applied to reference clock signals which are harmonically related and are used to generate harmonically related output clock signals.

Integrated jitter compliant clock signal generation

A phase difference between a reference clock signal and a feedback signal is digitally detected. A resultant phase detection signal is digitally filtered, and a PLL (Phase Locked Loop) output signal is synthesized in a fractional synthesizer under control of the digitally filtered phase detection signal. A feedback path, which could include an integer divider and/or a fractional N divider, provides the feedback signal based on the PLL output signal. The combination of a wide bandwidth fractional synthesizer and a low bandwidth digital PLL provides for a low bandwidth jitter filtering function with a wide bandwidth PLL to suppress VCO (Voltage Controlled Oscillator) noise and crosstalk.

Integrated jitter compliant low bandwidth phase locked loops

Signal timing phase selection and timing acquisition apparatus and techniques are disclosed. A timing phase that is most closely aligned with a phase of information carried by a received signal is selected from a plurality of timing phases. The selected timing phase may be used, for example, as a reference signal for a phase detector in a Phase-Locked Loop (PLL). The received signal may be sampled one or more times per timing phase. In a multiple-sample implementation, the samples may be used for timing phase selection, for detection of a known initial pattern of a burst of information to thereby detect the start time of a an information burst, or both.

Signal timing phase selection and timing acquisition apparatus and techniques

The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.

Linear burst mode synchronizer for passive optical networks

An eye opener circuit is provided which performs a data re-timing/eye opening function on a data signal after having been corrupted by jitter. The circuit uses a PLL driven by a clock source which was the same clock source used in timing the data signal originally. The PLL generates a local clock used to re-time the data. A phase error may be introduced into the PLL, or into the data signal.

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Ottawa, Canada

Shawn Lawrence Scouten