International Business Machines Corporation

Shawn Kollesar

Jesse Peter Surprise

Gerald Strevig, Iii

Christopher J Berry

Adam P Matheny

Michael Kazda

Chris Aaron Cavitt

Chaobo Li

Nany H Kollesar

Dina Hamid

Methods, systems and computer program products for improved placement of a clock gating latch are provided. Aspects include identifying a clock gating latch that is designated to control a local clock buffer. Aspects also include determining a plurality of data latches that are designated to be controlled by the local clock buffer. Aspects also include determining positions of the plurality of data latches within a layout. Aspects also include determining a position of the clock gating latch within the layout based on the positions of the plurality of data latches within the layout.

Clock gating latch placement

Methods, systems and computer program products for improved metal fill shape removal from selected nets are provided. Aspects include determining a first set and second set of timing characteristics of a first and second circuit design, respectively. The first circuit design does not include metal fill shapes around a plurality of nets, whereas the second circuit design does include metal fill shapes around a plurality of nets. Aspects also include identifying a set of candidate nets based on a comparison of the first set of timing characteristics to the second set of timing characteristics. The set of candidate nets are nets that are candidates for metal fill shape removal. Aspects include generating a third circuit design by removing one or more metal fill shapes positioned around each net of the set of candidate nets that are positioned within a radius of removal.

Metal fill shape removal from selected nets

Methods, systems and computer program products for providing cross-hierarchical block pin placement are provided. Aspects include designating potential pin placements by aligning output pins of each of a first set of bottom-level hierarchical blocks positioned within one or more middle-level hierarchical blocks to an edge of a respective middle-level hierarchical block. Responsive to determining that each of a first subset of a second set of bottom-level hierarchical blocks having input pins that correspond to the output pins of the first set of bottom-level hierarchical blocks are positioned within a respective middle-level hierarchical block that has a cross hierarchical alignment, aspects include placing pins at one or more of the potential pin placements. Aspects also include placing a set of pins based on aligning input pins of a second subset of the second set of bottom-level hierarchical blocks to an edge of a respective middle-level hierarchical block.

Cross-hierarchical block pin placement

Methods, systems and computer program products for providing wire orientation-based latch shuddling are provided. Aspects include determining a classification of each latch of a plurality of latches as having a vertical orientation, a horizontal orientation or a mixed orientation. Aspects also include clustering the plurality of latches into one or more clusters based on the classifications of the plurality of latches. Each of the one or more clusters includes a unique set of latches of the plurality of latches. Aspects also include shuddling each of the one or more clusters around a local clock buffer within a layout. Each cluster of the one or more clusters is shuddled in a configuration around the local clock buffer based on the classifications of the corresponding unique set of latches of the plurality of latches.

Wire orientation-based latch shuddling

A system to develop an integrated circuit includes a child placement module that places in a parent macro a child macro that contains therein a child logic circuit component. The parent macro has a first hierarchical level assigned thereto and the child macro has a lower second hierarchical level assigned thereto. The system further includes a timing analysis module and a component targeting module. The timing analysis module detects a timing fault in response to performing a first parent-level optimization process on the parent macro. The component targeting module extracts from the child macro a targeted logic circuit component and places the targeted logic circuit component in the parent macro. The timing analysis module performs a second parent-level optimization process on the parent macro that resolves the timing fault based on the placement of the targeted logic circuit component in the parent macro.

Multi-level hierarchical large block synthesis (hLBS) latch optimization

Methods, systems and computer program products for providing improved placement and connectivity of local clock buffer controllers are provided. Aspects include determining positions of a plurality of centroid locations within a circuit design based on positions of a plurality of latches within the circuit design. Aspects also include modifying the circuit design to place a local clock buffer controller at each of the plurality of centroid locations within the circuit design. Aspects also include connecting each of a plurality of local clock buffers within the circuit design to a nearest local clock buffer controller.

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Poughkeepsie, NY, United States of America

Shawn Kollesar