Globalwafers Co., Ltd.

Freescale Semiconductor,inc.

Asm America, Inc.

Asm IP Holding B.v.

Sunedison Semiconductor Limited (uen201334164h)

Shawn George Thomas

Gang Wang

Jeffrey Louis Libbert

Igor Peidous

Qingmin Liu

Srikanth Kommu

Arash Abedijaberi

Bich-Yen Nguyen

Ted R White

Mariam G Sadaka

Chun-Li Liu

Voon-Yew Thean

Alexander L Barr

Lu Fei

Andrew Marquis Jones

Alex Usenko

Marius K Orlowski

Nyles Wynn Cody

Alexander Barr

Mark R Hawkins

William L Luter

Henry Frank Erk

Matthew G Goodman

John Allen Pitney

Pierre Tomasini

Charles Robert Lottes

Philip J Tobin

Tab Allen Stephens

Papu D Maniar

Matthias Bauer

Eric R Hill

Vida Ilderem

John M Grant

Dejan Jovanovic

Matthew W Stoker

Qianghua Xie

Andrew M Jones

Charles R Lottes

A liner assembly for a substrate processing system includes a first liner and a second liner. The first liner includes an annular body and an outer peripheral surface including a first fluid guide. The first fluid guide is curved about a circumferential line extending around the first liner. The second liner includes an annular body, an outer rim, an inner rim, a second fluid guide extending between the outer rim and the inner rim, and a plurality of partition walls extending outwardly from the second fluid guide. The second fluid guide is curved about the circumferential line when the first and second liners are positioned within the processing system.

Liner assemblies for substrate processing systems

A susceptor including a generally circular body having a face with a radially inward section and a radially outward section proximate a circumference of the body, the radially outward section having at least one ring extending upward for contacting a bottom surface of a substrate, and wherein the radially inward section lacks a ring extending upward from the face.

Susceptor with ring to limit backside deposition

Methods for removing an oxide film from a silicon-on-insulator structure are disclosed. The oxide may be stripped from a SOI structure before deposition of an epitaxial silicon thickening layer. The oxide film may be removed by dispensing an etching solution toward a center region of the SOI structure and dispensing an etching solution to an edge region of the structure.

Methods for preparing a SOI structure

A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

High resistivity semiconductor-on-insulator wafer and a method of manufacture

A preheat ring () for use in a chemical vapor deposition system includes a first portion and a second portion selectively coupled to the first portion such that the first and second portions combine to form an opening configured to receive a susceptor therein. Each of the first and second portions is independently moveable with respect to each other.

CVD apparatus

A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of SiGe, SiC, SiGeSn, SiGeSnC, GeSn, group IIIA-nitrides, semiconductor oxides, and any combination thereof.

High resistivity SOI wafers and a method of manufacturing thereof

Methods for removing an oxide film from a SOI structure and methods for preparing a SOI structure

A multilayer semiconductor on insulator structure is provided in which the handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted by the handle substrate free carriers, thereby resulting in a high apparent resistivity, which improves the function of the structure in RF devices.

High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency

High resistivity semiconductor-on-insulator wafer and a method of manufacturing

An improved exhaust system for a gas-phase reactor and a reactor and system including the exhaust system are disclosed. The exhaust system includes a channel fluidly coupled to an exhaust plenum. The improved exhaust system allows operation of a gas-phase reactor with desired flow characteristics while taking up relatively little space within a reaction chamber.

Gas-phase reactor and system having exhaust plenum and components thereof

Growing community of inventors

Chesterfield, MO, United States of America

Shawn George Thomas