Texas Instruments Corporation

Microsemi Corporation

Shawn Anthony Fahrenbruch

Hugh Thomas Mair

Dror Korcharz

Arkadiy Peker

Liming Xiu

Bruce Ferguson

John L Wallberg

Simon Kahn

Lundy Findlay Taylor

George Y Liu

Ekrem Cengelci

Steven L Dondershine

A safety mechanism for a solar cell group, the safety mechanism constituted of: a signal receiver arranged to assert a permissive signal indicative of reception by the signal receiver of a predetermined signal; an electronically controlled switch arranged to provide in a closed state an effective short circuit across the output of the solar cell group responsive to the absence of the asserted permissive signal of the signal receiver; and a power harvester in communication with the solar cell group and arranged to provide electric power to the signal receiver when the electronically controlled switch is the closed state.

Photo-voltaic safety de-energizing device

A backlight system for light emitting diodes (LEDs), the backlight system constituted of: a controllable power source; a plurality of LED based luminaires arranged to receive power in parallel from the controllable power source; a plurality of driving circuitries, each of the plurality of driving circuitries arranged to control the light output of at least two of the plurality of LED based luminaires and further arranged to output information regarding the voltage drop of at least one of the at least two LED based luminaires controlled thereby, wherein the controllable power source is arranged to output a voltage whose value is responsive to the output information.

Distributed architecture voltage controlled backlight driver

A low voltage drop unidirectional electronic valve constituted of: a first terminal; a second terminal; a first electronically controlled switch coupled between the first terminal and the second terminal; and a first charge pump arranged to close the first electronically controlled switch when the voltage potential at the first terminal is greater than the voltage potential at the second terminal by a first value. The first charge pump is arranged in a closed loop with the first electronically controlled switch so as to continuously maintain the voltage potential at the first terminal greater than the voltage potential at the second terminal by the first value.

Low voltage drop closed loop unidirectional electronic valve

A method to generate a substantially DC output having a voltage level different than a DC input, constituted of receiving a feedback signal representing at least one of the voltage level and the current level of the generated substantially DC output; relatively emphasizing the high frequency portion of the feedback signal; controlling the buck function of a cascaded buck-boost converter with a first switching signal having a first duty cycle, the first duty cycle being a first function of the received feedback signal responsive to said relatively emphasized high frequency portion; and controlling the boost function with a second switching signal having a second duty cycle, the second duty cycle being a second function of the received feedback signal, wherein the first switching signal and the second switching signal are continuously enabled to facilitate a continuous conduction mode.

Method and apparatus for modifying right half-plane zero in a cascaded DC-DC buck-boost converter

A current-mode switching regulator uses adaptive current sensing to reliably monitor an inductor current in a cost-efficient and power-efficient manner. A semiconductor switch periodically turns on to conduct the inductor current. A voltage drop across the semiconductor switch is monitored when the semiconductor switch is on. A variable gain amplifier with an automatic gain control loop generates a feedback signal from the voltage drop of the semiconductor switch when conducting to provide an indication of the inductor current to a controller. The automatic gain control loop compensates for any variations in the on-resistance of the semiconductor switch.

Automatic gain control technique for current monitoring in current-mode switching regulators

A linear regulator circuit to regulate an output voltage includes a first current path to conduct a first current, a feedback path to provide feedback to maintain the output voltage at a constant voltage, and a transistor positioned in the first current path to provide the output voltage.

Linear regulator enhancement technique

A circuit is designed with a register circuit ( ) arranged to store a control word. A voltage-controlled oscillator ( ) is coupled to receive the control word ( ) and produce a clock signal ( ) having a current frequency corresponding to the control word. A phase detector circuit ( ) is coupled to receive a reference signal ( ) and the clock signal. The clock signal has one of a phase lead and a phase lag with respect to the reference signal. The phase detector circuit produces a phase signal ( ) having a first state in response to the phase lead and having a second state in response to the phase lag. An estimate circuit ( ) is coupled to the register circuit and the phase detector circuit. The estimate circuit produces a next control word ( ) corresponding to a next frequency intermediate the current frequency and a frequency corresponding to a transition between the first and second states.

Digital phase-locked loop with phase optimal frequency estimation

An electronic system, such as a video decoder (,), includes a clock generator circuit (,) based upon a phase-locked loop (PLL) (,). The PLL (,) includes a voltage controlled oscillator (VCO) (,) that produces a plurality of evenly-spaced output phases, each of a locked frequency relative to a reference clock (CREF). A frequency synthesis circuit (,) receives a frequency selection value on control lines (FREQ) that include an integer and a fraction portion. The integer and fraction portion of the frequency selection value are added to the current contents of a register (,) that stores the previous integer value used to select the corresponding phase from VCO (,) for application to the clock input of a toggle flip-flop (,) from which the output clock (COUT) is generated. Use of the fraction portion permits a time-averaged clock frequency to be produced with more precision than the multiple phases output by the VCO (,). Alternative embodiments include multiple frequency synthesis circuits (,) based upon the same PLL (,), and the generation of a phase-shifted secondary output from a phase synthesis circuit (,) that is slaved to the frequency synthesis circuit (,). Additional performance is obtained by providing separate paths (,) for producing the leading and trailing edges of the output clock (COUT).

Precision frequency and phase synthesis

An apparatus for producing a clock signal includes a recirculating delay-locked loop operable to receive a reference clock signal, produce an output clock signal, and adjust the relative phase, with respect to the reference clock signal, of the output clock signal to align the output clock signal with the reference clock signal. The apparatus also includes a phase filter that is operable to receive the output clock signal and filter any phase shift of the output clock signal over a plurality of cycles of the output clock to produce an adjusted output clock signal.

Post-filtered recirculating delay-locked loop and method for producing a clock signal

An emitter-coupled logic to CMOS logic converter includes a first current mirror having a first transistor that has a terminal. The first current mirror is operable to mirror a current in the terminal of the first transistor to produce a mirrored first current. The converter also includes a first current sink operable to generate a first current in the terminal of the first transistor. The converter also includes a second current mirror having a second transistor that has a terminal. The second current mirror is operable to mirror a current in the terminal of the second transistor to produce a mirrored second current. The converter further includes a second current sink operable to generate a second current in the terminal of the second transistor and a differential input pair operable to receive a differential voltage input and direct a current, based on the differential voltage input, to the terminal of the first transistor or the terminal of the second transistor. In addition, the converter includes a third current mirror for mirroring the first mirrored current and the second mirrored current to produce an output voltage that varies in response to changes in the differential voltage input.

Emitter-coupled logic to CMOS logic converter and method of operation

A ring oscillator includes a plurality of inverting delay elements connected in a ring. Each inverting delay element includes an inverter having an output node. The oscillator also includes a programmable current circuit operable to rob a variable amount of current from the output node of the inverter to control the duration of a delay period associated with the delay element.

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Tustin, CA, United States of America

Shawn Anthony Fahrenbruch