Agere Systems Inc.

Lucent Technologies Inc.

Agere Systems Guardian Corp.

Shaun Patrick Whalen

Michael Richard Betker

John Susantha Fernando

Hyun K Lee

Frederick Harrison Fischer

Kenneth Daniel Fitch

Avinash Velingker

Jay Patrick Wilshire

James Frank Vomero

Bryan Schlieder

Sucheta Sudhir Chodnekar

Pramod Vasant Argade

Han Nguyen

Harold J Wilson

Frank Lemmon

Stefan Thurnhofer

Algernon P Henry

Frank T Lemmon

A processor comprises memory circuitry and processing circuitry coupled to the memory circuitry. The processing circuitry is operative to retrieve from the memory circuitry an interrupt polling instruction which causes selection of an active enabled interrupt and generation of an interrupt vector for the selected active enabled interrupt. In conjunction with the selection and generation operations, an execution context of a program thread is stored in the memory circuitry, the stored execution context being utilizable to resume the program thread at an appropriate time subsequent to interruption of that thread.

Processor with instruction-based interrupt handling

A packet, cell or other data segment received in a physical layer device from a link layer device via an interface bus is processed to determine a port address for the data segment in the physical layer device. The port address, which may be an MPHY address, is determined using a combination of a first address value obtained from a link layer address portion of the data segment and a second address value obtained from a payload portion of the data segment. The data segment is stored in a memory location identified by the port address. The memory location may comprise a particular queue of the physical layer device.

Port addressing method and apparatus for link layer interface

Techniques are disclosed for implementing software breakpoints in a processor system having at least one processor coupled to a main memory and associated with an instruction cache. A breakpoint code is inserted at a particular location in the instruction cache of at least a given one of the processors, and a control indicator associated with the particular location is set to a first state which allows the breakpoint code to be returned to the given processor from the instruction cache in response to a first fetch request directed to a corresponding address. Subsequently, the control indicator associated with the particular location is set to a second state which directs that a second fetch request to the corresponding address be serviced from the main memory. The control indicator state is then changed again after a determination has been made, from the control indicator having been set to the second state, that the second fetch request to the corresponding address will be serviced from the main memory.

Processor system with cache-based software breakpoints

Techniques are disclosed for implementing software breakpoints in a multiprocessor system having a number of processors each coupled to a main memory. In an illustrative embodiment, each of the processors has an instruction cache associated therewith. An instruction for which a breakpoint is to be inserted is retrieved from a corresponding instruction address in the main memory, and a breakpoint code is inserted at the instruction address in main memory. After the breakpoint code is executed by a given one of the processors, the retrieved instruction is stored in the corresponding instruction cache for that processor, and a use-once indicator is set. The use-once indicator is operative via cache control logic to clear a validity indicator associated with the instruction after a single fetch of the instruction from the instruction cache, such that subsequent attempts by the given processor to access the instruction as stored in the instruction cache will cause the processor to retrieve the breakpoint code at the instruction address in main memory.

Multiprocessor system with cache-based software breakpoints

A virtually parallel multiplier-accumulator (VMAC) that can execute more than or less than one MAC operation in a single system clock cycle. The inventive VMAC advantageously employs a resource/time-sharing methodology with multiple sequential computational stages.

Virtually parallel multiplier-accumulator

A virtual parallel multiplier-accumulator (VMAC) that can execute more than or less than one MAC operation in a single system clock cycle. The inventive VMAC advantageously employs a resource/time-sharing methodology with multiple sequential computational stages.

Virtual parallel multiplier-accumulator

A method and apparatus allowing two independent arbiters which do not directly talk to one another to function on a common system bus, allowing efficient operation of a master controller, and virtually endless capability to add peripherals to the common system bus without problems or major modifications commonly associated with additional arbitration overhead. A master controller sets time slot parameters for an external, subordinate arbiter as often as desired. Based on the time slot parameter information, the subordinate arbiter functions on an electrically separated portion of the common system bus during all times but for a time slot associated with communication of the super arbiter over the entire common system bus. During this time, a tri-state buffer element allows communication between portions of the common system bus. In an adaptive arbitration mode, the subordinate arbiter combines static time slot information assigned in configuration registers together with actual bus requests to generate grant signals to the requesting devices, and reassigns all or portions of time slots which, although assigned to a particular device, are left unused for the relevant system cycle. A historical buffer may be maintained for any or all time slots. Using this historical information, long term statistical information may be generated. Moreover, the master controller may re-tune time slot configurations based on the historical information regarding past recent use of the relevant time slots.

Hierarchical bus arbitration

A method and apparatus allowing efficient access control to a common data bus by including an isolation device to separate the common data bus, a priority-based arbiter to control access to the internal portion of the common data bus including a processor or other bus master, and a time slot arbiter to control access to the external portion of the common data bus including multiple bus masters, an external memory interface, etc. The common external memory may be allocated for exclusive or non-exclusive use by the various devices utilizing either portion of the isolated common data bus. External devices accessing the external memory may communicate directly with one or more bus masters, e.g., on the internal portion of the common data bus.

Shared devices and memory using split bus and time slot interface bus arbitration

An apparatus and method that speeds the processing of data vectors in a digital processor is disclosed. In accordance with the present invention, a vector zero overhead loop with parallel issue processes multiple data elements at the same time, and yet is programmed with readable assembly language and requires neither vector registers nor a lot of extra registers to implement.

Accelerating vector processing using plural sequencers to process multiple loop iterations simultaneously

The present invention is embodied in a method and apparatus for generating a complete discontinuity trace of instruction execution by a digital processor utilizing a serial interface, such as a JTAG, that provides &ldquo;trace until&rdquo; capability by utilizing circular buffering of an on-chip discontinuity trace. The serial bit stream is observed as it is clocked out of the processor pins and trace codes are extracted and written to a local memory. Codes that have a complete address are arranged into a linked list, and the link information is used to maintain a circular buffer when the buffer fills up and the oldest data is overwritten with new data.

Apparatus and method for circular buffering on an on-chip discontinuity trace

A first register stores a value that can be used as a pointer to indirectly address a second register. The first register is referred to as a pointer register and the pointer as a register pointer. The second register may be a conventional register that stores a conventional register value (i.e., a data value or a pointer to a data value stored in external memory) or another pointer register. In certain embodiments, a pointer register can also be used to store conventional register values. Pointer registers of the present invention can be used to implement efficiently certain types of digital processing, such as circular buffers, vector processing, convolutional processing, and partitioned processing, using data in registers rather than memory.

Pointer register indirectly addressing a second register in the

A method and apparatus are disclosed for powering-up a microprocessor in a system under debugger control. The microprocessor comprises I/O connection pins, internal logic, and a reset condition responsive to a reset signal. Additionally, the microprocessor has a boundary scan architecture, such as an IEEE 1149.1 (JTAG) compliant interface, which includes a boundary scan register (BSR) and at least one design-specific test data register. The BSR has normal and test modes. In the normal mode, the BSR operatively connects the internal logic to the I/O connection pins. In the test mode, the BSR operatively isolates the internal logic from the I/O connection pins. The method comprising first detecting when power is applied to the microprocessor. Once power is detected and while the microprocessor remains in the reset condition, the BSR is put into tile test mode to isolate the internal logic from the I/O connection pins. Next, the debugger controls the microprocessor via the data register of the JTAG interface, conducting the necessary functions pursuant to power-up. Once the power-up functions are performed and the reset signal is disasserted, the internal logic can be reconnected with the I/O connection pins by returning the BSR to its normal mode.

Method for powering-up a microprocessor under debugger control

The invention specifies on-chip address matching hardware which is external to the processor core and prefetch queue of a microcontroller, and instruction decoding logic to mark and process breakpointed instructions. The address matching hardware includes a number of equality comparators which observe addresses on an intermodule bus of the microcontroller. This bus is not directly connected to the processor core and handles both instruction and data traffic. In one embodiment, four such matchers are provided. When an instruction address matches one of the breakpoints, a code indicating the breakpoint number is returned along with the instruction fetched. This breakpoint code is entered into the prefetch queue in the processor core, along with the instruction. When that instruction reaches the decode stage, the breakpoint information is decoded along with the instruction. The breakpoint actions associated with an instruction only occur when the instruction is about to be issued for execution. The decode logic of the processor core uses additional signals from the external matching hardware to determine if the breakpoint number associated with the current instruction is enabled to cause a breakpoint event. If the instruction is enabled to cause an event, the decode logic causes the event to happen. Regardless, the decode logic signals the external matching logic that a breakpointed instruction has been detected. When a breakpoint event is not enabled, the external matching logic can take other action such as updating a counter or starting execution monitoring activities.

Apparatus and method for decoding instructions marked with breakpoint

An integrated circuit having a digital processor, a decode stage for decoding an instruction from the instruction set, an execute stage coupled to the decode stage for executing the instruction, and event logic coupled to the decode stage operable to provide an event commands to the decode stage to override the instruction. In one embodiment, an integrated circuit having a pipelined processor handles multiple precise events through the decode stage and execute stage through a process which includes the steps of detecting a plurality of events and issuing an event command, selecting a highest priority event from said the of events, providing an event vector and a link address for the highest priority event, and allowing the event vector and the link to be modified for a higher priority event until the event command is issued to the execute stage.

Method and apparatus for uniform and efficient handling of multiple

A digital microprocessor having a processor core is provided with trace recording hardware capable of receiving, analyzing and temporarily storing data indicative of program instructions (i.e., instruction types) executed by the processor core and of their respective addresses. The trace recording hardware outputs an abbreviated real-time program trace, containing minimum data necessary to reconstruct a full program trace, via a JTAG port to an external debug host computer where a user may reconstruct the full program trace with reference to a program listing. The abbreviation scheme used by the trace recording hardware is preferably achieved by comparing instruction types received from the processor core to at least one pre-defined instruction type, and abbreviating or discarding the corresponding address information as a function of the particular instruction type. The trace recording hardware may be set into one of two modes by the user. In the first mode, the trace recording hardware stalls the processor core when it reaches its maximum storage capacity for instruction type and/or address data until storage becomes available. In the second mode, when the trace recording hardware becomes full it discards data received from the processor core and stores an overflow indicator. The program trace may be initiated and stopped by the user or by signals internal to the digital microprocessor.

Growing community of inventors

Wescosville, PA, United States of America

Shaun Patrick Whalen