Industrial Technology Research Institute

National Taiwan University

Shau-Yin Tseng

Tai-Hua Lu

Chih-Wei Hsu

Tei-Wei Kuo

Yuan-Hao Chang

Jia-Ming Chen

Chun-Lung Lin

Juin-Ming Lu

Chien-Hung Lin

Tzu-Chieh Shen

Yu-Sheng Lee

Yung-Chao Chen

Tsung-Ling Hwang

Ka-Yi Yeh

I-Hsuan Lu

Yi-Hsuan Fan

Che-Wei Tsao

Yan-Jen Su

Jin-Nan Liu

Chien-Wei Chen

Hsu-Yao Huang

Chihhao Chang

Chih-Chung Lu

Jian-Wei Chen

A method for generating and updating position distribution graph comprises: generating a position distribution graph according to a circuit bitmap and an exposure pattern, performing an exposure simulation according to the position distribution graph to generate an exposure result graph, comparing the circuit bitmap with the exposure result graph to generate a plurality of error distribution candidate graphs, selecting one of the error distribution candidate graphs to serve as an error distribution graph, and performing a zero-one integer programming to update the position distribution graph according to the circuit bitmap and the error distribution graph, wherein the updated position distribution graph is associated with the error distribution graph.

Method and system for generating and updating position distribution graph

A memory page management method is provided. The method includes receiving a state-change notification corresponding to a state-change page, and grouping the state-change page from a list to which the state-change page belongs into a keep list or an adaptive LRU list of an adaptive adjusting list according to the state-change notification; receiving an access command from a CPU to perform an access operation to target page data corresponding to a target page; determining that a cache hit state is a hit state or a miss state according to a target NVM page address corresponding to the target page, and grouping the target page into the adaptive LRU list according to the cache hit state; and searching the adaptive page list according to the target NVM page address to obtain a target DRAM page address to complete the access command corresponding to the target page data.

Memory controller and memory page management method

A method for compensating a design image of a workpiece and a system for processing the design image of the workpiece are disclosed. The method includes the following steps. Obtaining a real image of the workpiece, with the real image having registration holes. Calculating a slope value for each of the registration holes. Determining an amount of interpolation points between each two neighboring registration holes of the registration holes according to the slope value corresponding to each of the registration holes. Obtaining positions of control points in blocks formed by the registration holes. Compensating the design image of the workpiece according to positions of the registration holes, positions of the plurality of interpolation points and the positions of the control points for generating a mapping image. Outputting the mapping image adapted to be mapped onto the workpiece. The system, together with the method, will be introduced.

Method for compensating design image of workpiece and system for processing design image of workpiece

A method and a system for digital direct imaging, an image generating method and an electronic device are provided. The method for digital direct imaging includes: obtaining a first image of a first format; converting the first image into a second image of a second format, wherein the second image includes a contour description; generating a correction parameter according to at least one mark on a substrate; correcting the second image according to the contour description and the correction parameter; and performing a rasterization operation on the corrected second image and imaging the second image processed by the rasterization operation on the substrate by an exposure device.

Method and system for digital direct imaging, image generating method and electronic device

An exposing method adapted to a maskless photolithography process. The exposing method includes reading an exposure file; obtaining a plurality of coordinate information corresponding to a plurality of patterns contained in the exposure file, according to the exposure file; generating graphical data, according to the plurality of coordinate information; generating scanning data corresponding to each of a plurality of polygon mirrors or each of at least one polygon mirror group, according to the graphical data and a configuration of the polygon mirrors, wherein every two rotation directions of every two adjacent polygon mirrors of the plurality of polygon mirrors are different, or every two rotation directions of every two adjacent polygon mirrors of the at least one polygon mirror group are different.

Exposing method, exposing system and laser direct imaging system

A data-processing apparatus and an operation method thereof are provided. The data-processing apparatus includes a tiling circuit and a post-stage processing circuit. The tiling circuit is configured to receive input data. The tiling circuit divides a current frame of the input data into at least one tile and checks a motion state of the current tile in the at least one tile. The post-stage processing circuit is coupled to the tiling circuit to receive the current tile. The post-stage processing circuit performs post processing on the current tile to generate a processed current tile of the current frame or to obtain a processed corresponding tile of a previous frame and serves it as the processed current tile of the current frame, according to the motion state of the current tile.

Data-processing apparatus and operation method thereof

An exemplary embodiment describes a method for tile elimination, including: reading in data of a new tile; reading signature values corresponding to the new tile from a signature value repository; generating signature values for the new tile; comparing the read signature values and the generated signature values of the same tile to determine whether the two sets of signature values being identical; when the two sets of signature values being identical, copying the new tile directly from a tile frame buffer without rendering; otherwise, updating the signature value repository with the generated signature values replacing the stored signature values; rendering the tile; and updating the tile frame buffer with the newly rendered tile.

Apparatus and method for tile elimination

An apparatus and a method for performing video decoding processes in parallel are provided. The method is adapted for utilizing a first cluster and a second cluster of a processor to perform the video data decoding process in parallel. The method includes performing a VLD process to the video data with the first cluster, so as to obtain a plurality of coefficients and then performing an IZ process, an IQ process, and an IDCT process to the coefficients with the second cluster, so as to obtain a plurality of pixels values of the video data. When the first cluster decodes a coefficient of the video data, the second cluster performs the IZ, IQ, and IDCT processes to a coefficient previously decoded by the second cluster of the video data. Accordingly, a parallel process is realized and the decoding speed is increased.

Apparatus and method for performing video decoding processes in parallel

Disclosed is a power aware method and apparatus of video decoder on a multi-core platform. The power aware apparatus comprises a power management unit, and a processor unit having an entropy decoder and a decoder. The processor unit has at least one voltage and at least one frequency. One processor of the multi-core platform performs the entropy decoding for a frame, collects the entropy decoded information, and computes the decompressing time. Based on the computed decompressing time, the processor sets up the voltage and frequency for other or all processors to reduce power consumption for video decoders.

Power aware method and apparatus of video decoder on a multi-core platform

An apparatus for encryption and decryption, capable of use in encryption and decryption of advanced encryption standard. Byte substitution operation and inverse byte substitution operation are to be combined. Byte substitution operation can be expressed as y=M*multiplicative_inverse(x)+c while inverse byte substitution operation can be expressed as x=multiplicative_inverse(M*(y+c)), wherein M and Mare inverse matrix of each other and c is a constant matrix. Since the two equations employ a look-up table, that is, multiplicative_inverse(x), the lookup tables for use in byte substitution and inverse byte substitution operations are to be combined according to the invention so as to lower hardware complexity of the implementation. In addition, main operations of column mixing operation and inverse column mixing operation are to be rearranged to combine the two operations in part, resulting in simplified hardware implementation.

Growing community of inventors

Hsinchu County, Taiwan

Shau-Yin Tseng