Marvell International Limited

Marvellworld Trade Ltd.

Degirum Corporation

Stmicroelectronics S.a.

Marvell Asia Pte., Ltd.

Marvell Lnternational Ltd.

Shashi Kiran Chilappagari

Gregory Burd

Nedeljko Varnica

Xueshi Yang

Dung Viet Nguyen

Phong Sy Nguyen

Zhengang Chen

Viet-Dzung Nguyen

Winston Lee

Kit Sang Tam

David Declercq

Bane Vasic

Shiva Kumar Planjery

A computer system including a plurality of SIMD engines and a corresponding plurality of output register sets. Operand A register file stores one or more Operand A values, each including a plurality of operand words. Operand B register file stores one or more Operand B values, each including a plurality of operand words. Operand A distribution circuit receives an Operand A value from the Operand A register file, and selectively routes one or more of the operand words of the received Operand A value to create a plurality of input Operand A values, which are selectively routed to the SIMD engines. Operand B distribution circuit receives one or more Operand B values from the Operand B register file, and selectively routes one or more of the operand words of the Operand B value(s) to create a plurality of input Operand B values, which are selectively routed to the SIMD engines.

Method and apparatus for performing matrix multiplication

A computer system for performing negative sampling, including a processor chip having a plurality of on-chip memory banks, a plurality of on-chip compute engines and a memory interface, wherein the on-chip memory banks include memory blocks that store corresponding sets of 'likely to be updated' word vectors, a memory block that stores a subset of 'less likely to be updated' word vectors and a noise sample cache that stores a subset of negative samples. An external memory is coupled to the memory interface, and stores a set of &#x2018;less likely to be updated&#x2019; word vectors and a set of negative samples. The on-chip compute engines include a refresh thread, which accesses the set of negative samples in the external memory to provide the subset of negative samples stored in the noise sample cache on the processor chip, such that these negative samples can be readily accessed on the processor chip.

Word2VEC processing system

Systems and methods are provided for decoding a codeword having a first codeword length using a decoding system. The systems and methods include receiving a vector corresponding to the codeword at the decoding system, wherein the decoding system comprises a first decoder and a second decoder, the first decoder is available to concurrently process codewords up to the first codeword length, and the second decoder is available to concurrently process codewords up to a second codeword length. The systems and methods further include determining that the received vector is to be decoded using the second decoder, partitioning the received vector of the first codeword length into a plurality of segments having a size no larger than the second codeword length, and decoding the plurality of segments using the second decoder.

Systems and methods for using decoders of different complexity in a hybrid decoder architecture

Systems and methods for decoding a product code is provided. The system comprises a media, a first buffer, a second buffer, and a decoder. The media stores a plurality of codewords of a first code of the product code. The first buffer temporarily stores at least one codeword that has failed to be decoded. The second buffer temporarily stores soft information to be used in decoding. The decoder is configured to decode the plurality of codewords, determine if a first count of the at least one failed codeword exceeds a designed maximum number of codewords recoverable using the decoding method. In response to determining that the first count does not exceed the predefined threshold, the decoder iteratively process each failed codeword of the at least one failed codeword with the soft information, and attempt to decode at least one of each failed codeword that has been iteratively processed.

Systems and methods for iterative coding of product codes in nand FLASH controllers

System and methods described herein includes a method for iterative decoding. The method includes instantiating an iterative decoding procedure to decode a codeword. At each iteration of the iterative decoding procedure, the method further includes retrieving information relating to a plurality of current decoding variables at a current iteration, determining a first current decoding variable to be skipped for the current iteration based on the information, and processing a second decoding variable without processing the first decoding variable to update related decoding variables from the plurality of current decoding variables.

Systems and methods for an iterative decoding scheme

Systems and methods are disclosed for storing codewords in NAND memory. The method includes receiving a first and second codeword. The method includes storing a partition of the first codeword and a partition of the second codeword in a buffer. The method includes transferring the partition of the first codeword and the partition of the second codeword to a page in NAND memory.

Methods and systems for wordline based encoding and decoding in NAND flash

Systems and methods for performing a parity check on encoded data are disclosed. Encoded data is received. A parity check is performed based on a parity check matrix. In response to determining the first parity check is successful, a parity check number is incremented. Additional parity checks are selectively performed on subsequent portions of the array based on comparing the incremented parity check number to a threshold.

Systems and method for bit-flipping decoders with partial-column processing, ordering and scheduling

A decoding method decodes data iteratively according to a first rule, measures at a selected iteration at least one performance criterion of the decoding of data according to the first rule, performs at the selected iteration a comparison of the at least one performance criterion to a threshold, when the comparison yields a first result relative to the threshold, continues decoding according to the first rule, and when the comparison yields a second result relative to the threshold, continues decoding according to a further rule. Decoding apparatus operates according to the method. The decoding according to the first rule, the measuring at least one performance criterion at the selected iteration, the performing the comparison at the selected iteration, and the continuing decoding according to the first or further rule, may be repeated until the comparison yields a predetermined result. Repeating may be stopped after a predetermined maximum number of iterations.

Iterative decoder with dynamically-variable performance

Systems and methods are provided for decoding a codeword of a low density parity check (LDPC) code. The systems and methods may include receiving a vector corresponding to the codeword encoded with a parity check matrix, and processing a first portion of the received vector with a first portion of the parity check matrix to obtain a decoding estimate of a first portion of the codeword. The systems and methods may further include processing the decoding estimate of the first portion of the codeword with a second portion of the parity check matrix to obtain an intermediate vector, and processing a second portion of the received vector with a third portion of the parity check matrix and the intermediate vector to obtain a decoding estimate of a second portion of the codeword.

Systems and methods for decoding cascade LDPC codes

Systems, devices, and techniques relating to signal decoding are described. A describe device includes decoder circuitry configured to selectively update variable and check nodes to decode received information associated with a codeword, and selectively update a first group of the variable nodes and a first group of the check nodes in a first clock cycle; and look ahead circuitry configured to access, in the first clock cycle, a second group of the check nodes that are associated with a second group of the variable nodes, and generate node selection information, based on the second group of the check nodes, to indicate whether one or more variable nodes of the second group of the variable nodes are to be skipped or processed by the decoder circuitry in a second clock cycle based on their respective one or more likelihoods of being changed.

Decoders with look ahead logic

Systems and methods are provided for iterative data decoding. Decoding circuitry receives a first message from a variable node at a check node. Decoding circuitry generates a second message based at least in part on the first message. Decoding circuitry transmits the second message to the variable node. Decoding circuitry updates a hard decision value of the variable node based at least in part on the first message and the second message.

Systems and methods for hybrid message passing and bit flipping decoding of LDPC codes

A system including a first module, a second module and a third module. The first module is configured to generate a first parity check matrix. The second module is configured to append an appended matrix to the first parity check matrix to generate a resultant parity check matrix. The appended matrix includes additional elements. The third module is configured to receive user data and encode the user data based on the resultant parity check matrix.

System and method for encoding user data with low-density parity-check codes with flexible redundant parity check matrix structures

A decoder including a compression module configured to select one or more nodes from a plurality of nodes associated with data being decoded by the decoder, where each node includes one or more bits, and to compress the one or more bits associated with the selected nodes. A memory is configured to store the compressed one or more bits associated with the selected nodes.

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San Jose, CA, United States of America

Shashi Kiran Chilappagari