Cadence Design Systems, Inc.

Shashank Tripathi

Naresh Kumar

Prashant Sethia

Amit Dhuria

Umesh Gupta

Arvind Nembili Veeravalli

Jeannette Sutherland

Ritika Govila

A netlist of a multiple voltage circuit design having a plurality of power domains is established, then inter-power domain (IPD) paths traversing the circuit design are identified, according to whether they traverse multi-supply elements, or are clock paths capturing such a path. The netlist is then pruned to disable or remove cells or stages not traversed by an IPD path. A timing analyzer conducts a multi-domain timing analysis of the IPD timing paths in the pruned IPD netlist. Thereby, the circuit design is thoroughly tested according to the applicable ranges of voltage conditions without excessive runtime.

Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic

A static timing analysis method for input/output modes of an integrated circuit design, that includes loading the integrated circuit design described in a hardware description language into a memory. An active zone for static timing analysis is defined, which comprises logic and interconnect between an input/output port and a selected level of sequential logic elements upstream from an input port and downstream from an output port. A description of the active zone is generated using the hardware description language. Then a static timing analysis is performed on the logic of the active zone.

High performance static timing analysis system and method for input/output interfaces

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Ghaziabad, India

Shashank Tripathi