Sun Microsystems, Inc.

Shashank Shastry

Ajay Bhatia

Sanjay M Wanzakhade

Sagar V Reddy

A hybrid dual match line circuit may include a hit match line coupled to a first group of load devices and a miss match line coupled to discharge through a second group of load devices. Both the hit and miss match lines may be configured to be precharged to an asserted state. Each of the second group of load devices may be activated for discharging by a respective miss signal. The hit match line may be additionally coupled to discharge through first and second discharge path respectively activated for discharging in response to a hit signal and a read/write enable signal. The hit and miss match lines may be electrically isolated from one another, such that when one or more of the respective miss signals are asserted, current from the hit match line does not discharge through the miss match line.

Hybrid dual match line architecture for content addressable memories and other data structures

Dual match line circuits having race condition improvements. A dual match line circuit may include precharge logic configured to precharge each of a hit match line, a miss match line and an evaluate node to an asserted state, where a coupling device couples the hit and miss match lines to the evaluate node. The miss match line may discharge through a number of load devices that may be activated by respective miss signals. A positive feedback circuit coupled to the miss match line may accelerate its discharge. The hit match line may be additionally coupled to discharge through a discharge path. The hit and miss match lines may be electrically isolated from one another, such that when any of the respective miss signals is asserted, current from the hit match line does not discharge through the miss match line.

Race condition improvements in dual match line architectures

A dual match line circuit may include precharge logic configured to precharge each of a hit match line, a miss match line and an evaluate node to an asserted state, where a coupling device couples the hit and miss match lines to the evaluate node. The miss match line may discharge through a number of load devices that may be activated by respective miss signals. The hit match line may be additionally coupled to discharge through a pair of devices connected in series, one of which may be activated by a hit signal, and the other of which may be activated by the miss match line. The hit and miss match lines may be electrically isolated from one another, such that when any of the respective miss signals is asserted, current from the hit match line does not discharge through the miss match line.

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Santa Clara, CA, United States of America

Shashank Shastry