Cadence Design Systems, Inc.

Shashank Prasad

Naresh Kumar

Sushobhit Singh

Beenish

Ankur Gulati

Anil Kumar Mishra

Vishal Karda

The present disclosure relates to a system for performing static timing analysis in an electronic design. Embodiments may include providing, using at least one processor, an electronic design and extracting hierarchical crossing path exception information from a hierarchical design view associated with the electronic design. Embodiments may further include transferring the hierarchical crossing path exception information to a block view associated with the electronic design and extracting a timing model based upon, at least in part, the hierarchical crossing path exception information. Embodiments may also include implementing the timing model at a top-level view associated with the electronic design.

Systems and methods for extracting hierarchical path exception timing models

The present disclosure relates to a computer-implemented method for assigning pins in an electronic design. The method may include generating a pin list associated with the electronic design, the pin list having a one or more pins that are directly and indirectly connected with at least one of a master partition and a clone partition. The method may further include sorting one or more pins within the pin list based upon, at least in part, a number of local connections to generate a sorted pin list and selecting a first pin having a highest number of local connections of the sorted pin list as a reference pin. The method may also include selecting a partition of the reference pin, as a reference partition and identifying one or more alignment zones for every connected pair of pins in the sorted pin list. The method may further include transforming all alignment zones to the reference partition using a depth-first-search.

System, method, and computer program product for pin assignment in an electronic design

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Noida, India

Shashank Prasad