Silicon Laboratories Inc.

Sandisk Technologies Inc.

Cadence Design Systems, Inc.

Sharon Mutchnik

Mitchell Grant Poplack

Hendricus De Ruijter

Hitesh Gannu

Moshe Gat

Boris Liubovitch

Ramesh Mogili

An emulation system comprises an outband traffic generating device comprising at least one field programmable gate array coupled to a host system. The outband traffic generating device is configured to transfer one or more bits via an outband channel to a register of an inband traffic generating device. The inband traffic generating device comprises at least one field programmable gate array coupled to a target system. The inband traffic generating device is configured to transfer the one or more bits via an inband channel to the outband traffic generating device.

Method and system to transfer data between components of an emulation system

A system may include date flow module circuits configured between electronic devices or circuits that may affect and/or intercept the flow of data being communicated between electronic devices. The data flow module circuits may communicate with an external controller that may want to intervene in the data communication. The data flow module circuits may be configured in a pass mode or in an intervention mode. In the pass mode, a data flow module circuit may pass on data it receives without intervention by the external controller. In the intervention mode, the data flow module circuit may receive instructions from the external controller as to the data that the external controller wants the data flow module to output.

Data flow circuits for intervention in data communication

A technique includes receiving a datum indicative of a candidate delimiter in a receiver; and processing the datum in a machine to determine whether the datum indicates a synchronization delimiter. The processing includes comparing the candidate delimiter with a reference delimiter to identify at least one error in the candidate delimiter; and basing the determination of whether the datum indicates the synchronization delimiter at least on a bit position of of each error.

Method and apparatus to detect a synchronization delimiter

An adaptive synchronous FIFO includes a plurality of input data latch stages that sample variable-length input data at a write clock frequency, and a data compression circuit that combines the variable-length input data, together with partial-row data from a row of the FIFO storage array, and writes the combined data at a read clock frequency. The number of data latch stages is adaptive according to the ratio of the read and write clock frequencies.

Adaptive FIFO

An apparatus includes a signal processing circuit and at least two oscillators that provide, respectively, at least first and second reference signals. The apparatus further comprise a selection circuit. The selection circuit provides to the signal processing circuit one of the first and second reference signals depending on a mode of operation of the signal processing circuit.

Apparatus for providing reference signals and associated methods

In a particular embodiment, a forward error correction (FEC) decoder is disclosed that includes an input responsive to a communication channel to receive sampled bits from a continuous bit stream. The circuit device further includes a logic circuit to alternately provide sets of the received sampled bits from the continuous bit stream to one of a first syndrome generator and a second syndrome generator to correct errors in the sets of sampled bits to produce a decoded output related to the continuous bit stream.

Multi-syndrome error correction circuit

A method and circuit are shown for decoding a Manchester encoded data input signal, wherein preamble found, data input, and recovered clock signals are received and a phase of the data input signal stored responsive thereto. A decision time signal alternates state responsive to the recovered clock signal. A switch pulse signal asserts when the decision time signal is active and the stored phase and current phase of the data signal have the same logic value, which is stored and cleared responsive to the recovered clock signal. A data output is decoded from a decision pair of phases responsive to the recovered clock, preamble found and decision time signals. The stored and current phases of the data input signal are selected to be the decision pair when neither the switch pulse signal or stored switch pulse signal are asserted and, otherwise, the stored phase and inverted stored phase are selected.

Growing community of inventors

San Jose, CA, United States of America

Sharon Mutchnik