Hewlett-packard Development Company, L.p.

Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Compaq Information Technologies Group, L.p.

Sharon Marie Britton

Daniel Lawrence Leibholz

James Arthur Farrell

Derrick R Meyer

Bruce Alan Gieseke

Harry Ray Fair, Iii

Timothy Charles Fischer

Sridhar Samudrala

Randy Allmon

A technique for managing register assignments. The technique involves maintaining, in a register list memory circuit having entries that respectively correspond to physical registers, a list of register assignments that assign logical registers to the physical registers. The technique further involves maintaining, in a vector memory circuit having bits that respectively correspond to the physical registers, a valid vector that forms, in combination with the list of register assignments, a list of valid register assignments. Furthermore, the technique involves storing, for an instruction that is mapped by the data processor, a copy of the valid vector from the vector memory circuit to a silo memory circuit. Preferably, the processor using the technique has the ability to execute branches of instructions speculatively, and to recover if it is determined that the processor executed down an incorrect instruction branch.

Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list

Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list

A technique for processing register instructions in a pipeline data processor in which multiple instructions may be processed concurrently, and may therefore conflict with one another. Register instructions are identified with register groups indicating which processor registers are affected by the execution of the register instruction. The progress of the execution of the register instruction is then controlled depending upon the identified register groups, in order to avoid conflicts with other concurrently processed instructions.

Technique for ordering internal processor register accesses

A circuit is provided for using the input operands of a floating point addition or subtraction operation to detect the leading one or zero bit position in parallel with the arithmetic operation. This allows the alignment to be performed on the available result in the next cycle of the floating point operation and results in a significant performance advantage. The leading I/O detection is decoupled from the adder that is computing the result in parallel, eliminating the need for special circuitry to compute a carry-dependent adjustment signal. The single-bit fraction overflow that can result from leading I/O misprediction is corrected with existing circuitry during a later stage of computation.

Leading one/zero bit detector for floating point operation

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Westboro, MA, United States of America

Sharon Marie Britton