Qualcomm Incorporated

Sharon Graif

Lior Amarilio

Tomer Rafael Ben-Chen

Navdeep Mer

Richard Dominic Wietfeldt

Lalan Jee Mishra

Radu Pitigoi-Aron

Sriharsha Chakka

Meital Zangvil

Naveen Kumar Narala

Kishalay Haldar

Mark Gakman

Amit Gil

Yiftach Benjamini

Shaul Yohai Yifrach

Jason R Gonzalez

Mouna Elkhatib

Punit Kishore

Yossi Amon

Prashanth Kumar Kakkireni

Ben Levin

Viney Kumar

Oren Nishry

Ghanashyam Prabhu

David Asher Friedman

Sai Ganapathy Srinivasan

Systems, methods, and apparatus are configured to enable a receiver to provide feedback. In one example, a method performed at a device coupled to a serial bus includes receiving a write command from the serial bus in a datagram, writing a data byte received in a first data frame of the datagram to a register address identified by the datagram, and using a second data frame of the datagram to provide feedback regarding the datagram. Feedback may be provided by driving a data line of the serial bus to provide a negative acknowledgement during the second data frame when a transmission error is detected in the datagram, and refraining from driving the data line of the serial bus during the second data frame when no transmission error is detected in the datagram, thereby providing an acknowledgement of the datagram.

Providing acknowledgements for system power management interface

High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.

High-speed communication link with self-aligned scrambling

Systems and methods for fast activation of slaves during wake up in an audio system allow a master device in an audio system such as a SOUNDWIRE audio system to send system and/or topology information to capable slave devices during a wake up window so that the slaves may start in an active mode rather than a safe mode. In the most recent proposed versions of SOUNDWIRE, there is a check PHY_Num phase. The systems for fast activation of slaves cause a negative differential line to be driven with an encoded signal by the master during a check PHY_Num phase where the encoded signal indicates a fast mode speed. Capable slaves may then begin in a fast mode rather than a safe (and slow) mode. Latency may be reduced by starting in a fast mode, which may improve the user's audio experience.

Fast activation during wake up in an audio system

Systems, methods, apparatus and techniques are described that provide point-to-point capabilities without the expected increase in input/output pad usage. In some examples, point-to-point data lines are provided between a host and multiple slave devices and timing of communication is controlled using a clock signal shared by the multiple slave devices. An apparatus has a plurality of bus master circuits configured to control point-to-point communication with corresponding slave devices and a clock generation circuit configured to provide pulses in a serial bus clock signal when one or more bus master circuits are in an active state, and further to idle the serial bus clock signal when all bus master circuits are idle. Each bus master circuit may be configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal that is transmitted over a common clock line to each slave device.

I2C bus architecture using shared clock and dedicated data lines

Systems, methods, and apparatus for power management are disclosed. A power management integrated circuit has a bus interface circuit configured to couple the power management integrated circuit to a shared communication bus, one or more regulator circuits configured to provide current to a managed device, and a controller. The controller is configured to determine that current consumption by the managed device exceeds a threshold level, generate an extended current level message to be transmitted over the shared communication bus to the managed device and transmit a time value with the extended current level message, the time value indicative of an elapsed time between generation of the extended current level message and start of transmission of the extended current level message.

Extended current limit message latency aware performance mitigation

Systems, methods, and apparatus are configured to enable a receiver to provide feedback. A feedback mechanism enables a transmitting device to identify the provider of feedback for a multicast transmission, and the feedback transmitted by one or more individual receivers of the multicast transmission. A method includes receiving a multicast write command from the serial bus in a first datagram, writing a data byte received in a first data frame of the first datagram to a register address identified by the first datagram, and providing device-specific feedback regarding the first datagram in a multibit slot within the second data frame. The multibit slot is one of a plurality of sequential multibit slots defined for the second data frame. Each multibit slot in the plurality of sequential multibit slots may provide device-specific feedback from one receiving device addressed by the multicast write command.

Group slave identifier time-multiplexed acknowledgment for system power management interface

The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.

Hang correction in a power management interface bus

The disclosure includes systems and methods for bus control. A method comprises receiving a data exchange request, wherein the data exchange request includes a data exchange tag that identifies a data exchange, splitting the data exchange into a plurality of fractional data transactions, providing one or more bus commands to a system bus, receiving, at the bus controller, one or more acceptance notifications indicating that the one or more of the plurality have been accepted by the system bus, assigning transaction identifiers (TIDs) corresponding to the one or more of the plurality of fractional data transactions, receiving one or more completion notifications indicating that the one or more of the plurality have been completed, determining that each of the plurality of fractional data transactions associated with the data exchange tag have been completed, and notifying the processor that the requested data exchange has been completed.

Bus controller and related methods

The systems and methods for bus ownership in a system power management interface (SPMI) bus may include two or more masters on the SPMI bus, and bus ownership may be passed between masters. The current owner of the bus is responsible for providing a clock signal on the clock line of the SPMI bus. To avoid problems caused by ringing of the clock signal being sent on a conductor that exceeds the SPMI specification, the original master (from whom bus ownership is being transferred) holds the clock line of the SPMI bus at a logical low for a clock delay value that is based on conductor length.

Bus ownership for a system power management interface (SPMI) bus

Systems and methods for scrambling data-port audio in SOUNDWIRE&#x2122; systems include a scramble enable feature that allows a data source to scramble an outgoing channel content with a cyclic linear feedback shift register (LFSR) using a pseudo-random binary sequence (PRBS) such as, but not limited to, the PRBS defined in the SOUNDWIRE specification. Data ports for audio sinks receiving the scrambled content descramble the content for use by the audio sink. In a specific exemplary aspect, an output of the LFSR is added or subtracted with the audio data to make the microphones independent of one another and reduce crosstalk.

Scrambling data-port audio in SOUNDWIRE systems

Methods and apparatuses for aggregated IBIs are provided. The apparatus includes a host controller configured to communicate with at least one slave via a serial communication bus, trigger and receive a series of responses from the at least one slave via the serial communication bus, determine one response of the series of responses indicating an in-band interrupt (IBI) request, and respond to the IBI request based on a position of the one response among the series of responses. The method includes communicating with at least one slave via a serial communication bus, triggering and receiving a series of responses from the at least one slave via the serial communication bus, determining one response of the series of responses indicating an in-band interrupt (IBI) request, and responding to the IBI request based on a position of the one response among the series of responses.

Aggregated in-band interrupt based on responses from slave devices on a serial data bus line

Systems, methods, and apparatus are described. A method for data communication performed at a master device includes configuring a serial interface for a point-to-point mode of operation, transmitting a first two-bit command through the serial interface, the two-bit command including a one-bit address and a read/write bit, and initiating a transaction through the serial interface. The transaction may be identified by the two-bit command and is conducted in accordance with an I3C protocol. The transaction may include the transfer of one or more data frames formatted in accordance with the I3C protocol. The method may include receiving an acknowledgement from a slave device in response to the first two-bit command.

I3C point to point

A method of in-system structural testing of a system-on-chip (SoC) using a peripheral interface port is described. The method including enabling a scan interface controller of the SoC through the peripheral interface port. The method also includes streaming structural test patterns in the SoC through the scan interface controller.

In-system structural testing of a system-on-chip (SoC) using a peripheral interface port

Systems, methods, and apparatus for communicating virtual GPIO information generated at multiple source devices and directed to multiple destination devices. A method performed at a device coupled to a serial bus includes generating first virtual GPIO state information representative of state of one or more physical GPIO output pins, asserting a request to transmit the first virtual GPIO state information by driving a data line of the serial bus from a first state to a second state after a start code has been transmitted on a serial bus and before a first clock pulse is transmitted on a clock line of the serial bus, transmitting the first virtual GPIO state information as a first set of bits in a data frame associated with the start code, and receiving second virtual GPIO state information in a second set of bits in the data frame.

Growing community of inventors

Zichron Yaakov, Israel

Sharon Graif