Applied Materials Israel Limited

Sharon Duvdevani-Bar

Roman Kris

Grigory Klebanov

Einat Frishman

Vadim Vereschagin

Elad Sommer

Assaf Shamir

Ishai Schwarzband

Rafael Bistritzer

Shimon Levi

Ilan Ben-Harush

Dhananjay Singh Rathore

Sahar Levin

Jannelle Anna Geva

Efrat Noifeld

Tal Orenstein

Daniel Alan Rogers

Meir Vengrover

Ido Friedler

Noa Marom

Avi Aviad Ben Simhon

Meng Li Cecilia Lim

Roi Meir

Hiroshi Miroku

Kasturi Saha

Taku Yoshizawa

A method for process control of a semiconductor structure fabricated by a series of fabrication steps, the method comprising obtaining an image of the semiconductor structure indicative of at least two individual fabrication steps; wherein the image is generated by scanning the semiconductor structure with a charged particle beam and collecting signals emanating from the semiconductor structure; and processing, by a hardware processor, the image to determining a parameter of the semiconductor structure, wherein processing includes measuring step/s from among the fabrication steps as an individual feature.

Method, system and computer program product for 3D-NAND CDSEM metrology

A method, non-transitory computer readable medium and an evaluation system for evaluating an intermediate product related to a three dimensional NAND memory unit. The evaluation system may include an imager and a processing circuit. The imager may be configured to obtain, via an open gap, an electron image of a portion of a structural element that belongs to an intermediate product. The structural element may include a sequence of layers that include a top layer that is followed by alternating nonconductive layers and recessed conductive layers. The imager may include electron optics configured to scan the portion of the structural element with an electron beam that is oblique to a longitudinal axis of the open gap. The processing circuit is configured to evaluate the intermediate product based on the electron image. The open gap (a) exhibits a high aspect ratio, (b) has a width of nanometric scale, and (c) is formed between structural elements of the intermediate product.

Evaluating an intermediate product related to a three-dimensional NAND memory unit

There is provided a system and method of generating a metrology recipe usable for examining a semiconductor specimen, comprising: obtaining a first image set comprising a plurality of first images captured by an examination tool, obtaining a second image set comprising a plurality of second images, wherein each second image is simulated based on at least one first image, wherein each second image is associated with ground truth data; performing a first test on the first image set and a second test on the second image set in accordance with a metrology recipe configured with a first parameter set, and determining, in response to a predetermined criterion not being met, to select a second parameter set, configure the metrology recipe with the second parameter set, and repeat the first test and the second test in accordance with the metrology recipe configured with the second parameter set.

Generating a metrology recipe usable for examination of a semiconductor specimen

An evaluation system that may include an imager; and a processing circuit. The imager may be configured to obtain an electron image of a hole that is formed by an etch process, the hole exposes at least one layer of a one or more sets of layers, each set of layers comprises layers that differ from each other by their electron yield and belong to an intermediate product. The processing circuit may be configured to evaluate, based on the electron image, whether the hole ended at a target layer of the intermediate product. The intermediate product is manufactured by one or more manufacturing stages of a manufacturing process of a three dimensional NAND memory unit. The hole may exhibit a high aspect ratio, and has a width of a nanometric scale.

Evaluating a hole formed in an intermediate product

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Mazkeret-Batya, Israel

Sharon Duvdevani-Bar