Cypress Semiconductor Corporation

Xilinx, Inc.

Sharmin Sadoughi

Krishnaswamy Ramkumar

Igor Polishchuk

Maroun Khoury

Ravindra Manohar Kapre

Pamela Shiell Trammel

Michael J Hart

Zhiyuan Wu

Mira Ben-Tzur

Jae-Gyung Ahn

John W Cooksey

Prabhuram Gopalan

Saurabh Dutta Chowdhury

Michal Efrati Fastow

Sang S Kim

Avner Shelem

A multi-fingered device can be calibrated for performance. The multi-fingered device can include a first finger configured to remain active and a second finger that is initially deactivated concurrent with the first finger being active. A measure of degradation for the multi-fingered device within an IC can be determined. The measure of degradation can be compared with a degradation threshold. Responsive to determining that the measure of degradation meets the degradation threshold, a finger of the multi-fingered device can be activated.

Calibrating device performance within an integrated circuit

Device features, such as gate lengths and channel widths, are selectively altered by first identifying those devices within a semiconductor die that exhibit physical attributes, e.g., leakage current and threshold voltage magnitude, that are different than previously verified by a design/simulation tool used to design the devices. The identified, non-conforming devices are then further identified by the amount of deviation from the original design goal that is exhibited by each non-conforming device. The non-conforming devices are then mathematically categorized into bins, where each bin is tagged with a magnitude of deviation from a design goal. The mask layers defining the features of the non-conforming devices are then selectively modified by an amount that is commensurate with the tagged deviation. The selectively modified mask layers are then used to generate a new semiconductor die that exhibits improved performance.

Method of product performance improvement by selective feature sizing of semiconductor devices

An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-stress dual stress liner NMOS device having a stress reduction layer that extends between the tensile stress layer and the NMOS gate film stack, and a reduced-stress dual stress liner PMOS device having a stress reduction layer that extends between the compressive stress layer and the PMOS gate film stack. In embodiments of the invention additional reduced-stress dual stress liner NMOS devices and reduced-stress PMOS devices are formed by altering the thickness and/or the material properties of the stress reduction layer.

Integrated circuit device with stress reduction layer

In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., Hor HO) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.

Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors

A semiconductor structure including a semiconductor substrate, an isolation trench in the semiconductor substrate, and an alignment trench in the semiconductor substrate is disclosed. The structure also includes a dielectric layer and a metallic layer. The dielectric layer is on the semiconductor substrate and in both the isolation trench and the alignment trench. The dielectric layer fills the isolation trench and does not fill the alignment trench. The metallic layer is on the dielectric layer.

Semiconductor structure having alignment marks with shallow trench isolation

A process for fabricating a semiconductor structure comprises depositing a nitride layer on a semiconductor substrate with a first tool, and depositing an anti-reflective layer on the semiconductor substrate with the first tool. The nitride layer includes silicon and nitrogen.

In situ deposition of a nitride layer and of an anti-reflective layer

A method and a system are provided for forming a borderless contact structure. In particular, a method is provided which includes using an inorganic anti-reflective coating layer as an etch stop to form a borderless contact structure. In some embodiments, the method may include patterning an interconnect line above an inorganic layer with anti-reflective properties and depositing an upper interlevel dielectric layer above the interconnect line. A trench may then be etched within the upper interlevel dielectric layer such that a borderless contact structure may be formed in contact with said interconnect line. Consequently, a semiconductor topography is provided, in such an embodiment, which includes an inorganic anti-reflective coating layer arranged below an interconnect line and a contact structure arranged upon the interconnect line. In some embodiments, a width of the contact structure may be greater than a width of the interconnect line.

Borderless contact architecture

A method of forming a field oxide or isolation region in a semiconductor die. A nitride layer (over an oxide layer disposed over a substrate) is patterned and subsequently etched so that the nitride layer has a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the nearly vertical sidewall of the nitride layer. A field oxide is then grown in the recess using a high pressure, dry oxidizing atmosphere. The sloped sidewall of the substrate effectively moves the face of the exposed substrate away from the edge of the nitride layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and a nearly non-existent bird's beak. The desirable range of slopes for the substrate sidewall is approximately 50&deg;-80&deg; with respect to a nearly planar surface of the substrate in the recess.

Method and structure for isolating integrated circuit components and/or semiconductor active devices

A method of forming a field oxide or an isolation region in a semiconductor die. An oxidation mask layer (over an oxide layer disposed over the substrate) is patterned and subsequently etched, preferably so that the oxidation mask layer may have a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the sidewall of the oxidation mask layer. A field oxide is then grown in the recess using a dry oxidizing atmosphere. The sloped sidewall of the substrate recess effectively moves the face of the exposed substrate away from the edge of the oxidation mask layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and less field oxide thinning. The preferred range of slopes for the substrate sidewall is from approximately 10.degree. to 40.degree. with respect to the oxidation mask layer sidewall.

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Menlo Park, CA, United States of America

Sharmin Sadoughi