Hitachi America, Ltd.

Advanced Micro Devices Corporation

Legerity, Inc.

Sharif Mohammad Sazzad

Larry Alan Pearlstein

Jagannathan Bharath

Frank Anton Lane

Tony E Sawan

Michael Allen Plotnick

Video decoder methods and apparatus are described. In accordance with the invention, hardware decoder circuitry, e.g., intra-coded image decoding circuitry and motion vector reconstruction circuitry, is used in combination with a general purpose processor, e.g., Pentium processor, to perform video decoding operations. The video decoder hardware circuitry of the present invention is responsible for performing non-memory intensive functions. The general purpose processor or a general purpose processor operating in conjunction with a graphics processor are used to perform memory intensive video decoding operations such as motion compensated predictions. The video decoding hardware circuitry of the present invention can be implemented as a separate physical device, e.g., chip, or can be implemented on the same physical chip as a general purpose processor with which it works. By using the video decoding hardware circuitry of the present invention in combination with a CPU, a computer system's ability to perform video decoding operations can be significantly increased at little cost in terms of additional hardware.

Methods and apparatus for decoding images using dedicated hardware circuitry and a programmable processor

Edge detection methods and apparatus which utilize the dc dct differential data included in encoded images, e.g., an MPEG-2 encoded video stream, are described. Use of the dc dct differential data allows efficient methods for detecting the presence of edges within encoded images. The edge detection methods and apparatus of the present invention can be used where differential coding of the DC DCT coefficients is employed. Accordingly, the edge detection methods of the present invention are applicable to MPEG-2 encoded images as well as other differentially encoded images.

Methods and apparatus for detecting edges within encoded images

Methods and apparatus for simulating, in reduced resolution video decoders, the biasing effect associated with MPEG's specified rounding of pixel values including a fractional component of 0.5 to the next highest integer value are described. In one embodiment, the biasing effect is simulated by generating luminance and chrominance DC DCT coefficient bias values from, e.g., motion vector offset data. The DC DCT bias values are then added to the DC DCT coefficients of the luminance and chrominance blocks, respectively, which correspond to the same image block to which the motion vector data used to generate the bias values corresponds. In another embodiment, pixel values are directly adjusted to simulate the biasing effect associated with MPEG compliant rounding. In such an embodiment, luminance and chrominance pixel biasing values are generated as a function of, e.g., motion vector offset information. The bias values are added to the pixel values generated through the use of motion compensated prediction. The pixel values are then rounded by performing a non-biased rounding operation to generate integer pixel values.

Methods and apparatus for reducing drift due to averaging in reduced resolution video decoders

Methods and apparatus for performing signed saturation of binary numbers to arbitrary powers of two are described. Given an n-bit signed binary word, the methods and apparatus of the present invention perform a signed saturation to k-bits where the value of k can vary such that 1<k<n. Through the use of hardware circuits of the present invention the signed saturation operation is implemented in a more efficient manner than software implementations which utilize multiple compare operations. The signed saturation circuits of the present invention can be incorporated into processors, e.g., CPUs, to provide a hardware implementation within a CPU for a signed saturation processor instruction, e.g., either a SISD OR SIMD saturation command or instruction. The signed saturation circuits can accept the data value upon which the operation is to be performed, and, optionally, a value k indicating the number of bits to which individual data value are to be saturated. In MPEG-2 decoding, at the end of the inverse quantization process the quantities being processed undergo signed saturation to 12-bits. In various embodiments, one or more signed saturation circuits of the present invention are incorporated into a fixed function hardware circuit that performs, for example, MPEG-2 video decoding to perform the saturation to 12 bits.

Methods and apparatus for performing a signed saturation operation

Methods and apparatus for implementing and using a sign(x) function are described. In accordance with the present invention, the sign(x) function is implemented in hardware, e.g., by incorporating a simple circuit of the present invention into a central processing unit (CPU). By taking a hardware approach as opposed to the known software approach to implementing a sign(x) function, the present invention provides for an efficient sign(x) function implementation that is well suited for both SISD and SIMD systems. The hardware required to implement the sign(x) function in accordance with the present invention is relatively simple and allows for the sign(x) function to be determined in a single processor clock cycle. This is in sharp contrast to the plurality of processor clock cycles normally required to determine the sign(x) function in software embodiments. A processor sign(x) command is supported in embodiments where the hardware for performing the sign(x) function is incorporated into a processor. By incorporating a single sign(x) circuit into a processor a SISD sign(x) function can be supported. By duplicating the basic sign(x) hardware within a processor, in accordance with the present invention, a SIMD sign(x) function can be implemented. The sign(x) hardware and novel sign(x) processor command of the present invention, can be used to facilitate a variety of applications where the sign(x) function is encountered.

Methods and apparatus for implementing and using processors with sign function capability

Methods and apparatus for implementing video decoders at a reduced cost are described. The methods include data reduction techniques, simplified inverse quantization techniques, and dynamically varying the complexity of image enhancement operations, e.g., prediction filtering operations, as a function of whether luminance or chrominance data is being processed. In order to reduce data storage requirements, luminance and chrominance data corresponding to previously encoded images may be stored at different resolutions with, in some embodiments, chrominance data being stored at less than half the resolution of luminance data. In various embodiments, data representing portions of B frames which will not be displayed is identified and discarded, e.g., without performing a decoding operation thereon. Portions of I and P frames which will not be displayed are identified and decoded at a reduced resolution and/or using simplified inverse quantization techniques. The decoded I and P frame data is stored for use when making subsequent predictions if required. Another data reduction technique involves applying different amounts of data reduction, e.g., downsampling, to different image portions with no or little downsampling being performed on image portions located at or nearest to the image's center of interest as determined from information included in a received encoded bitstream.

Methods and apparatus for processing luminance and chrominance image data

A memory-efficient system and method for generating data blocks &ldquo;on demand&rdquo; for TDMA data bursts. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded full-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator. The stream of bits from the multiplexer forms the bit reordered and frame interleaved data for the data blocks.

System and method for bit interleaving of full-rate speech data

Methods and apparatus for implementing a sign function

Methods and apparatus for implementing single instruction multiple data (SIMD) signal processing operations are described. The apparatus of the present invention include new registers and register arrays which allow data to be accessed at a word as well as sub-word or sub-register level. The registers and register arrays of the present invention may be used when implementing a system based on a SIMD architecture. Registers implemented in accordance with the present invention include a plurality of pass gates that allow an entire n-bit word stored in the register to be accessed and output as a single word or for a sub-word portion of a stored word to be accessed and output. During standard operation the registers are accessed on a word basis. However, during column access operations, e.g., when performing a transpose operation, access is performed on a sub-word basis. The ability to access the registers of the present invention on a word or sub-word level make implementing transpose and various other row/column data manipulation operations possible in a relatively straightforward manner without data buffering. In addition to the novel registers and register arrays of the present invention, various aspects of the present invention are directed to new and novel SIMD instructions, e.g., SIMD move, add, and move instructions, which support the specification of data to be processed as operands which identify rows or columns of register arrays as opposed to merely identifying registers as done with conventional commands. A transpose command is also supported.

Registers and methods for accessing registers for use in a single instruction multiple data system

Methods and apparatus for reducing the cost of video decoders

Methods and apparatus for combining linear image post-processing operations with an inverse discrete cosine transform (IDCT) operation are described. In accordance with various embodiments of the present invention IDCT and downsampling operations are combined into a single operation to achieve the same image processing result as sequential IDCT and downsampling operations. By combining the two operations and performing downsampling in the DCT, as opposed to pixel domain, significant complexity reduction is achieved over embodiments where the two operations are performed sequentially. In one particular embodiment, when interlaced images are being processed, combined IDCT/downsampling circuits which perform field based, as opposed to frame based, downsampling in the DCT domain are employed. The method and apparatus of the present invention can be used to implement circuits which perform a combined full order IDCT/downsampling operation and/or a reduced complexity combined full order IDCT/downsampling operation. The combined IDCT/downsampling methods and apparatus of the present invention are capable of supporting a wide range of downsampling ratios using, at least in some cases, fewer math operators, than are required to implement zonal filtering followed by a reduced order IDCT operation which requires the use of a contiguous subblock of DCT coefficients.

Methods and apparatus for combining downsampling and inverse discrete

Methods and apparatus for implementing video decoders at a lower cost than known video decoders are described. The methods include data reduction techniques, simplified inverse quantization techniques, and dynamically varying prediction filter complexity as a function of whether luminance or chrominance data is being processed. In various embodiments, data representing portions of B frames which will not be displayed is identified and discarded, e.g., without performing a decoding operation thereon. Portions of I and P frames which will not be displayed are identified and decoded at a reduced resolution and/or using simplified inverse quantization techniques. The decoded I and P frame data is stored for use when making subsequent predictions if required. Another data reduction technique involves applying different amounts of downsampling to different image portions with no or little downsampling being performed on image portions located at or nearest to the image's center of interest as determined from information included in a received encoded bitstream. Simplified inverse quantization techniques of the present invention which are suitable for use when processing data from P or B frames involve performing a simplified non-MPEG compliant inverse quantization operation. The inverse quantization operation of the present invention is implemented by treating an additive factor, k, as having a value of zero for both predictively and intra-coded data and/or by eliminating the mismatch control operation normally performed as part of an MPEG compliant inverse quantization operation.

Methods and apparatus for reducing the complexity of inverse

A memory-efficient system and method for generating data blocks 'on demand' for TDMA data bursts. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded full-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator. The stream of bits from the multiplexer forms the bit reordered and frame interleaved data for the data blocks.

A memory-efficient system and method for generating data blocks 'on demand' for TDMA data bursts. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded half-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator. The stream of bits from the multiplexer forms the bit reordered and frame interleaved data for the data blocks.

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Monmouth Junction, NJ, United States of America

Sharif Mohammad Sazzad