Qromis, Inc.

Shari Farrens

Cem Basceri

Vladimir Odnoblyudov

Ozgur Aktas

An engineered substrate structure includes a ceramic substrate having a front surface characterized by a plurality of voids, and a barrier layer encapsulating the ceramic substrate. The barrier layer defining a plurality of valleys corresponding to the plurality of voids. The engineered substrate structure further includes a first bonding layer comprising a bonding layer material and coupled to the barrier layer on the front surface of the ceramic substrate. The first bonding layer defines a plurality of fill regions filled with the bonding layer material in the plurality of valleys corresponding to the plurality of voids. The engineered substrate structure further includes a second bonding layer coupled to the first bonding layer, and a substantially single crystalline layer joined to the second bonding layer.

Polycrystalline ceramic substrate

An engineered substrate structure includes a ceramic substrate having a front surface characterized by a plurality of peaks. The ceramic substrate includes a polycrystalline material. The engineered substrate structure also includes a planarization layer comprising a planarization layer material and coupled to the front surface of the ceramic substrate. The planarization layer defines fill regions filled with the planarization layer material between adjacent peaks of the plurality of peaks on the front surface of the ceramic substrate. The engineered substrate structure further includes a barrier shell encapsulating the ceramic substrate and the planarization layer, wherein the barrier shell has a front side and a back side, a bonding layer coupled to the front side of the barrier shell, a single crystal layer coupled to the bonding layer, and a conductive layer coupled to the back side of the barrier shell.

Polycrystalline ceramic substrate and method of manufacture

A substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the first adhesion layer, a second adhesion layer coupled to the barrier layer, and a conductive layer coupled to the second adhesion layer. The substrate also includes a bonding layer coupled to the support structure, a substantially single crystal silicon layer coupled to the bonding layer, and an epitaxial semiconductor layer coupled to the substantially single crystal silicon layer.

Engineered substrate structures for power and RF applications

A substrate including a support structure. The support structure including a polycrystalline ceramic core and a first adhesion layer coupled to the polycrystalline ceramic core. The support structure further including a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier layer coupled to the second adhesion layer. The substrate further including a bonding layer coupled to the support structure. The substrate further including a substantially single crystal layer comprising at least one of silicon carbide, sapphire, or gallium nitride coupled to the bonding layer. The substrate further including an epitaxial semiconductor layer coupled to the substantially single crystal layer.

A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial layers by epitaxial growth on the epitaxial silicon layer.

Methods of manufacturing engineered substrate structures for power and RF applications

A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer encapsulating the polycrystalline substrate, and a bonding layer coupled to the barrier layer. The method further includes forming a first silicon layer coupled to the bonding layer, forming a dielectric layer coupled to the first silicon layer, forming a second silicon layer coupled to the dielectric layer, removing a portion of the second silicon layer and a corresponding portion of the dielectric layer to expose a portion of the first silicon layer, forming a gallium nitride (GaN) layer coupled to the exposed portion of the first silicon layer, forming a gallium nitride (GaN) based device coupled to the GaN layer, and forming a silicon-based device coupled to a remaining portion of the second silicon layer.

System for integration of elemental and compound semiconductors on a ceramic substrate

An interposer includes a polycrystalline ceramic core disposed between a first surface and a second surface of the interposer, an adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the adhesion layer, and one or more electrically conductive vias extending from the first surface to the second surface through the polycrystalline ceramic core, the adhesion layer, and the barrier layer.

Method and system for electronic devices with polycrystalline substrate structure interposer

A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial III-V layers by epitaxial growth on the epitaxial silicon layer.

A method of fabricating a ceramic substrate structure includes providing a ceramic substrate, encapsulating the ceramic substrate in a barrier layer, and forming a bonding layer coupled to the barrier layer. The method further includes removing a portion of the bonding layer to expose at least a portion of the barrier layer and define fill regions, and depositing a second bonding layer on the at least a portion of the exposed barrier layer and the fill regions.

A micro-electromechanical system (MEMS) device includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier layer coupled to the second adhesion layer. The support structure defines a cavity. The MEMS device also includes a III-V membrane coupled to a portion of the support structure. A portion of the III-V membrane is suspended over the cavity defined by the support structure and defines a MEMS structure.

Gallium-nitride based devices implementing an engineered substrate structure

A substrate includes a polycrystalline ceramic core; a first adhesion layer encapsulating the polycrystalline ceramic core; a conductive layer encapsulating the first adhesion layer; a second adhesion layer encapsulating the conductive layer; a barrier layer encapsulating the second adhesion layer, and a bonding layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the bonding layer.

Engineered substrate structure and method of manufacture

An electronic device includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier layer coupled to the second adhesion layer. The electronic device also includes a buffer layer coupled to the support structure, a contact layer coupled to the buffer layer, and a field-effect transistor (FET) coupled to the contact layer.

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Boise, ID, United States of America

Shari Farrens