Qualcomm Incorporated

Sharath Kumar Nagilla

Hithesh Hassan Lepaksha

Darshan Kumar Nandanwar

Venkata Biswanath Devarasetty

Nirav Narendra Desai

Sravan Kumar Ambapuram

Kumar Kanti Ghosh

Lakshmi Narayana Panuku

Venkatesh Ravipati

Chandrashekar Reddy Kunreddy

Shrikanth Shenoy

An interconnect controller is coupled to a cache and coupled to a plurality of masters and configured to receive a cache access packet from a master. The cache access packet includes a first master identifier to identify the master, a first sub-cache index identifier to identify a slice of the cache, and an operation to be performed on the cache. A mapping table has master identifiers associated with sub-cache index identifiers and compare logic compares the first master identifier and the first sub-cache index identifier to the mapping table. The interconnect controller rejects the cache access packet in response to the first master identifier not being associated with the first sub-cache index identifier in the mapping table.

Cache access rejection for unauthorized secure cache ID from known master

Systems and methods for reducing data movement when performing large-sized memory transactions in a memory hierarchy are provided. For certain preselected types of large-size memory transactions, such as memset and memcopy operations, for example, logic of the processor determines whether the type of memory transaction being queued is one of the preselected types for which alteration of the path of data movement is an option. Logic of the processor also determines whether the size of the memory block associated with the transaction is sufficiently large to warrant altering the path of data movement. If the type is one of the preselected types and the size of the memory block is sufficiently large, logic of the LLC controller selects an altered path for data movement that reduces data movement and performs the transaction using the altered path.

Methods and systems for altering the path of data movement for large-sized memory transactions

A method of execution unit (EU) sharing between processor cores is described. The method includes encountering a structural hazard associated with an issued instruction in an instruction queue of a dispatch stage inside an active processor core. The method also includes issuing a request for an idle execution unit of an inactive processor core. The method further includes sending a transaction containing source operands of the issued instruction, and a word address of a result buffer as a destination operand to an allocated EU of the inactive processor core. The method also includes replacing the issued instruction in the instruction queue with a load operation to forward a result of the issued instruction from the result buffer based on the word address.

Execution unit sharing between processing cores in a cluster of a system-on-chip (SoC)

Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting a number of cache lines that satisfy an eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways; selecting at least one cache way from the group for collapse, based on its corresponding number of cache lines that satisfy the eviction criteria; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

Performance aware partial cache collapse

Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting, in each cache way of a group of cache ways, a number of dirty cache lines having dirty bits indicating the cache line has been modified; selecting, from the group, at least one cache way for collapse, based on its corresponding number of dirty cache lines; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

Access optimized partial cache collapse

An apparatus sets an operating voltage of a shared power rail in a multi-core electronic device. The apparatus includes a system-on-chip (SoC) having multiple cores with each core in the SoC configured to report an operating status. The apparatus includes an operating state aggregator configured to receive the operating status reported from each core in the SoC and to select the selected operating voltage based on the operating status from each core. A voltage regulator is in communication with the operating state aggregator and a power management integrated circuit (PMIC). The selected operating voltage is then programmed into the (PMIC) to control the shared power rail.

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Hyderabad Telangana, India

Sharath Kumar Nagilla