Juniper Networks, Inc.

Sun Microsystems, Inc.

Sharada Yeluri

Jean-Marc Frailong

Jeffrey Glenn Libby

Anurag P Gupta

Shahriar Ilislamloo

John Keen

Kevin Clark

Avanindra Godbole

Jianhui Huang

Swamy Sadashivaiah Renu Kananda

Sri Karthik Goud Gadela

Rajesh Nair

Varkey Paul Alapat

Venkatraman Chandrasekaran

Raymond Scott Chan

Shunn-Cheng Jang

Nancy Y Shaw

Marc R Tremblay

Edwin Su

Chung Lau

Paul Coelho

Subramania Sudharsanan

Jeffrey Meng Wah Chan

Biyu Pan

An example first network device includes a control unit configured to execute at least one application and a forwarding unit. The forwarding unit includes an interface configured to receive packets, at least one packet processor operably coupled to a memory, and a forwarding path, wherein at least a portion of the forwarding path is stored in the memory and is executable by the at least one packet processor. The forwarding unit is configured to receive an advertisement originated by a second network device in a network, wherein the advertisement specifies a second micro segment identifier (SID), and store, in a destination lookup table, a route entry comprising a first micro SID associated with the first network device and the second micro SID.

Micro SID packet processing

A data read/write system includes a system clock, a single port memory, a cache memory that is separate from the single port memory, and a controller coupled to an instruction pipeline. The controller receives, via the instruction pipeline, first data to write to an address of the single port memory, and further receives, via the instruction pipeline, a request to read second data from the single port memory. The controller stores the first data in the cache memory, and retrieves the second data from either the cache memory or the single port memory during one or more first clock cycles of the system clock. The controller copies the first data from the cache memory and stores the first data at the address in the single port memory during a second clock cycle of the system clock that is different than the one or more first clock cycles.

Use of cache to reduce memory bandwidth pressure with processing pipeline

A device may emulate target instructions by executing a first set of microinstructions, and may store a base address of a table that includes a microinstruction provided in a second set of microinstructions for emulating the target instructions. The device may also locate the microinstruction based on the stored base address, and emulate one of the target instructions by executing the microinstruction.

Emulation of multiple instruction sets

Systems and methods of various embodiments provide mechanisms to support synchronous and asynchronous transactions. Distinct encodings allow an instruction to choose whether to perform any operation synchronously or asynchronously. Separate synchronous and asynchronous result registers hold the data returned in the most recent replies received for synchronous and asynchronous transaction requests, respectively. A status bit indicates whether an asynchronous transaction request is currently outstanding.

System and method for independent synchronous and asynchronous transaction requests

A system improves bandwidth used by a data stream. The system receives data from the data stream and partitions the data into bursts. At least one of the bursts includes one or more idles. The system selectively removes the idles from the at least one burst and transmits the bursts, including the at least one burst.

Merge systems and methods for transmit system interfaces

Methods and systems consistent with the present invention provide efficient packet replication in a router in order to multicast a stream of data. Packets are replicated and processed in a multithreaded environment. Embodiments consistent with the present invention implement a two-stage process for packet replication. The first stage thread will recirculate the packet to multiple second-stage threads. These second-stage threads will then create one or more outgoing copies of the packet. In this way, the copies are handled by multiple threads running in parallel.

System and method for efficient packet replication

Data units received by a network device may be classified into traffic flow classes in which the determined traffic flow class for a data unit may be dynamically refined as the data unit is processed by the network device. A dispatch component of the network device may receive data units associated with traffic flow classes. Parallel processing engines of the network device may receive the data units from the dispatch component and may generate, for a least one of the data units, a plurality of dynamically refined indications of the traffic flow class to which the data unit belongs. Additionally, an ordering component of the network device may include a plurality of re-order queues, where the at least one data unit successively progresses through at least two of the re-order queues in an order defined by the plurality of dynamically refined indications of the traffic flow class.

Maintaining data unit order in a network switching device

Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition codes to a branch offset. This technique allows for a flexible multi-way branching functionality, using a conditional branch outcome table that can be specified by a programmer. Any instruction can specify the evaluation of arbitrary conditional expressions to compute the values for the condition codes, and can choose a particular branching function. When the processor executes the instruction, the processor's arithmetic/logical functional units evaluate the conditional expressions and then the processor performs the branch operation, according to the specified branching function.

Branching to target address by adding value selected from programmable offset table to base address specified in branch instruction

Fast execution of branch instruction with multiple conditional expressions using programmable branch offset table

A method for emulating a nexthop instruction in microcode with the assistance of dedicated hardware to extract read and write addressing from the nexthop instruction instead of performing this operation in microcode. A method for emulating a nexthop instruction in microcode with the assistance of dedicated hardware to compare a nexthop read address to a special value and to indicate whether the nexthop read address matches the special value, instead of performing this operation in microcode. A method for determining a network address by performing a single extraction of bit fields of a tree instruction to allow multiple tree search processes to be performed.

Hardware support for instruction set emulation

A system balances bandwidth used by a data stream. The system receives data in the data stream and partitions the data into bursts. The system then identifies whether a size of a current one of the bursts is less than a size of a maximum burst associated with the data stream and schedules an additional burst in the data stream when the current burst size is less than the maximum burst size. The system transmits the current burst and the additional burst to balance bandwidth used by the data stream.

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San Jose, CA, United States of America

Sharada Yeluri