International Business Machines Corporation

Sharad P Gandhi

Eric P Kronstadt

Tushar R Gheewala

A microcomputer memory system is organized into a plurality of banks (16). Each back consists of an array of static column mode dynamic random access memories (DRAMs) of the type having an on-chip static buffer for storing an entire row. The static buffers associated with each bank functions as a distributed cache (24) to hold the last accessed row for the associated bank. A memory controller (18) receives real addresses from a CPU (10) or other device on the memory bus (14) and extracts bank and row numbers from the address. The memory controller determines whether the accessed row for a memory bank is in the distributed cache and, if it is, accesses the distributed cache for that bank. Otherwise, the memory controller switches the contents of the distributed cache with the contents of the addressed row for that bank.

Distributed cache in dynamic rams

A branch target table (10) is used as an instruction memory which is referenced by the addresses of instructions which are targets of branches. The branch target table consists of a target address table (12), a next fetch address table (14), valid entries table (16) and an instruction table (18). Whenever a branch is taken, some of the bits in the untranslated part of the address of the target instruction, i.e. the instruction being branched to, are used to address a line of the branch target table (10). In parallel with address translation, all entries of the branch target table line are accessed, and the translated address is compared to the target address table (12) entry on that line. If the target address table entry matches the target address, the instruction prefetch unit (32) fetches the instruction addressed by the next fetch address table (14) entry for the given line and the line of instructions associated with the branch address table entry is read into an instruction queue (38) having a length set by the valid entry table ( 16) entry which indicates how many of these instructions are valid. Otherwise, the instruction prefetch unit (32) fetches the target and subsequent instructions as it would if there were no branch target table, and the target address table entry is set to the real address of the target instruction. The next fetch address table (14) is updated so that it always contains the address of the instruction which follows the last valid instruction in the line, and the valid entries table (16) is updated so that it always counts the number of valid instructions in the line.

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Sharad P Gandhi