Qualcomm Incorporated

Texas Instruments Corporation

Western Digital Technologies, Inc.

Nvidia Corporation

Sharad Kumar Gupta

Rahul Sahu

Pradeep Raj

Mukund Narasimhan

Chulmin Jung

Rakesh Kumar Sinha

Veerabhadra Rao Boda

Priyankar Mathuria

Arun Kumar Shukla

Arunkumar Mani

Silky Mohanty

Athira Kanchiyil

Sunil Kumar Misra

Noor Mohamed

Jung Pill Kim

Vinod J Menezes

Shahid Ali

Dharin Nayeshbhai Shah

Adithya Bhaskaran

Thomas Meier

Bhanu Prashanthi Murthy

Jais Abraham

Lakshmikantha Holla Vakwadi

Vish Visvanathan

Chong Zhang

Sei Seung Yoon

Rashmi Sachan

Morris D Ward

Yunchen Qiu

Lakshmikantha V Holla

Shiba Narayan Mohanty

Santhosh Narayanaswamy

Akhtar Waseem Alam

Dharmesh Kumar Sonkar

Diwakar Singh

Akshdeepika

Narender Ponna

Anuroop S S R Vuppala

Hemant Patel

Karthik Vijayan

Karthik Vitjayan

Dharaneedharan Shanmugasundaram

A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

Memory with scan chain testing of column redundancy logic and multiplexing

A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

High-speed multi-port memory supporting collision

Apparatuses and methods to reduce leakage current are presented. The includes a switch circuit configured to power a circuit block; a delay circuit configured to delay enabling the switch circuit powering the circuit block and to be powered down; and a bypass circuit configured to bypass the delay circuit to disable the switch circuit powering the circuit block. The method includes powering, by switch, a circuit block; powering down a delay circuit; and bypassing, by a bypass circuit, the delay circuit to disable the switch circuit powering the circuit block.

Power supply circuit with reduced leakage current

One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.

Memory circuit architecture with multiplexing between memory banks

A level-shifting pulse latch is provided for a self-timed memory clock signal for a memory. The level-shifting pulse latch includes a system-power-domain-to-memory-power-domain level-shifter that inverts and level-shifts a system clock signal into an inverted version of the system clock signal. A pass transistor controls whether the inverted version of the system clock signal drives a memory-power-domain latch to produce the self-timed memory clock signal.

Low power and robust level-shifting pulse latch for dual-power memories

A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.

Memory with efficient DVS controlled by asynchronous inputs

According to certain aspects, a level shifter includes a first branch including a first pull-up transistor configured to pull up a first node, and a first pull-down transistor configured to pull down the first node. The level shifter also includes a second branch including a second pull-up transistor configured to pull up a second node, and a second pull-down transistor configured to pull down the second node. The level shifter further includes a third branch including a third pull-up transistor configured to pull up a third node, and a third pull-down transistor configured to pull down the third node. The first branch is cross coupled with the third branch, the second branch is cross coupled with the third branch, the first pull-down transistor has a first channel width, the second pull-down transistor has a second channel width, and the first channel width is greater than the second channel width.

Wide voltage range level shifter with reduced duty cycle distortion across operating conditions

Systems and methods for propagating control signals in memories are described. One implementation includes a plurality of logic gates and a latch coupled between a control signal input and a delay line. The latch may store the value of the control signal before the control signal floats, thereby reducing the risk of incorrect signal propagation. Furthermore, the implementation may also include a clamp signal that isolates the plurality of logic gates before the control signal floats and continues to isolate the plurality of logic gates until after the control signal returns to either a digital one or a digital zero. The clamp signal may reduce leakage by disconnecting transistors within the logic gates from their power supply.

Systems and methods for control signal latching in memories

Certain aspects of the present disclosure are directed to a memory circuit. The memory circuit generally includes a memory cell coupled between a bit-line and a complementary bit-line. The memory circuit also includes a first n-type metal-oxide-semiconductor (NMOS) transistor configured to couple the bit-line to a write drive input during a write cycle of the memory circuit. The memory circuit also includes a second NMOS transistor configured to couple the complementary bit-line to a complementary write drive input during the write cycle, and a multiplexer circuit having a first p-type metal-oxide-semiconductor (PMOS) transistor coupled between a voltage rail and the bit-line or the complementary bit-line, the multiplexer circuit being configured to couple, via the first PMOS transistor, the bit-line or the complementary bit-line to the voltage rail during the write cycle.

Write assist circuitry for memory

Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes a control circuit that controls data to be copied from a single level cell block of a plurality of single level cell blocks to at least two multi level cell blocks of a plurality of multi level cell blocks.

Reusing a cell block for hybrid dual write

Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes an allocation circuit that allocates a single level cell block of a plurality of single level cell blocks to a first stream in response to a multi level cell block of a plurality of multi level cell block being allocated to the first stream.

Cell block allocation for hybrid dual write

A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.

Area efficient write data path circuit for SRAM yield enhancement

Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

Access assist with wordline adjustment with tracking cell

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Bengaluru, India

Sharad Kumar Gupta