Marvellworld Trade Ltd.

Telegent Systems, Inc.

Synopsys, Inc.

Other

Koninklijke Philips Corporation N.v.

Marvell International Limited

Trident Microsystems (far East) Ltd.

Trident Microsystems, Inc.

Shaori Guo

Jeanne Q Cai

Xingzhi Wen

Yu Hong

Selliah Rathnam

Gwo Giun Lee

Hefei Zhu

Chien-Hsin Lin

Qunzhao Tian

Yan Zhang

Andrew J Burstein

Zhenyu Zhang

Shi Cheng

Jun Cao

Saleem Chisty Mohammad

Fei Ren

Subramaniam Aravindhan

Dongxin Zhou

Baolei Xie

Jigang Yang

Eric Hung

Chandrashekar B U

Zu Bing Yuan

Zubing Yuan

A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include sorting a subset of a plurality of endpoints for communication during a communication frame first based on service interval time assigned to each endpoint and then resorting based on a concurrency score of each peripheral device corresponding to the subset of the plurality of endpoints. The operations may include determining available bandwidth and a number of packets to be communicated with the each endpoint of the subset of the plurality of endpoints. The operations may include generating a scheduling table that includes the number of packets and an order of communication of the packets to be communicated with the each endpoint of the subset of the plurality of endpoints.

Method and apparatus for USB periodic scheduling optimization

Various embodiments are directed to a USB hub configured for supporting multiple data transfer speed protocols. The USB hub comprises a plurality of protocol/LINK layer components; and a physical layer component shared among the plurality of protocol/LINK layer components and supporting at least two USB connection ports. The physical layer component is in communication with each of the plurality of protocol/LINK layer components. A buffer system (including RX/TX buffers) is shared among the plurality of protocol/LINK layer components and a USB host controller component is in communication with the buffer system. The physical layer component is configured for operating in a first mode to support one of the at least two USB ports in a first operating mode; and operating in a second mode to support the at least two USB ports in a second operating mode.

Method and apparatus for increasing the number of USB root hub ports

A system includes a cache and a cache-management component. The cache includes a plurality of cache lines that correspond to a plurality of device endpoints. The cache-management component is configured to receive a transfer request block (TRB) for data transfer involving a device endpoint. In response to a determination that the cache both (i) does not include a cache line assigned to the device endpoint and (ii) does not include an empty cache line, the cache-management component assigns, to the device endpoint, a last cache line that includes a most recently received TRB in the cache, and stores the received TRB to the last cache line.

Systems and methods for cache management for universal serial bus systems

Systems and methods are provided for cache management. An example system includes a cache and a cache-management component. The cache includes a plurality of cache lines corresponding to a plurality of device endpoints, a device endpoint including a portion of a universal-serial-bus (USB) device. The cache-management component is configured to receive first transfer request blocks (TRBs) for data transfer involving a first device endpoint and determine whether a cache line in the cache is assigned to the first device endpoint. The cache-management component is further configured to, in response to no cache line in the cache being assigned to the first device endpoint, determine whether the cache includes an empty cache line that contains no valid TRBs, and in response to the cache including an empty cache line, assign the empty cache line to the first device endpoint and store the first TRBs to the empty cache line.

System and methods are provided for managing universal-serial-bus (USB) data transfers. An example system includes a non-transitory computer-readable storage medium including a first scheduling queue for sorting endpoints and a host controller. The host controller is configured to: store a plurality of endpoints for data transfers to the storage medium, an endpoint corresponding to a portion of a USB device; sort the plurality of endpoints in a first order; generate a first transmission data unit including multiple original data packets, the original data packets being allocated to the plurality of endpoints based at least in part on the first order; and transfer the first transmission data unit.

System method for managing USB data transfers by sorting a plurality of endpoints in scheduling queue in descending order based partially on endpoint frequency

Boot-up delay within a television receiver IC is substantially reduced by loading a portion of an operating program into the television receiver IC to enable execution of time-consuming receiver initialization operations, and then executing the receiver initialization operations concurrently with loading the remainder of the operating program into the television receiver IC. By this operation, the time required to execute the receiver initialization operations may be at least partly hidden under the time required to load the operating program, thereby substantially reducing the boot-up delay.

Fast-booting broadcast television receiver

A first device comprising a transceiver module configured to begin transmission of a first signal to a second device. A control module is configured to, in response to the transceiver module receiving a second signal during the transmission of the first signal to the second device, determine whether the second signal corresponds to crosstalk by having the transceiver module suspend the transmission of the first signal. In response to the transceiver module continuing to receive the second signal subsequent to the transceiver module having suspended the transmission of the first signal to the second device, the control module determines that the second signal does not correspond to crosstalk. In response to the transceiver module not continuing to receive the second signal subsequent to the transceiver module having suspended the transmission of the first signal to the second device, the control module determines that the second signal does correspond to crosstalk.

Method and apparatus for detecting crosstalk between a plurality of devices communicating in accordance with a universal serial bus (USB) protocol

A sequence of data packets is received within an integrated circuit device and stored within a first memory thereof. Error descriptor values are updated within a second memory of the integrated circuit device based on error information associated with the sequence of data packets. The error descriptor values each include an address field to specify a corresponding storage region of the first memory and an error field to specify an error status of data values stored within the storage region. A sequence of multiple-bit error values are generated based, at least in part, on the error fields and address fields within respective subsets of the error descriptor values. Concurrently with generation of at least one of the multiple-bit error values the state of one or more bits of the data values stored in the first memory based are changed based on a previously-generated one of the multiple-bit error values.

Pipelined error determination in an error-correcting communication system

Memory storage requirements for digital signal processing operations, for example, motion-compensated video scan rate conversion, that produce intermediate output data, which is then used as an input to the operation, are reduced by reordering operations and organizing memory allocations in a special manner to allow intermediate output at a particular execution time, to substantially share the same memory space as the intermediate output of a previous execution time. Such a reduction in the amount of memory required for processing operations advantageously reduces cost and power consumption.

Memory optimization for video processing

A first data packet is received within an integrated circuit device and stored within a first memory thereof starting at a first address that is determined by the size of one or more previously received data packets. An error descriptor value is updated within a second memory of the integrated circuit device, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies. A multiple-bit error value is generated based, at least in part, on the error descriptor, each bit of the multiple-bit error value corresponding to a respective storage location within a storage row of the first memory. The state of one or more bits within the storage row of the first memory are changed based, at least in part, on the multiple-bit error value.

Erasure generation in a forward-error-correcting communication system

According to an example embodiment, the present invention is directed to pixel-data processing that includes scanning a first 2&#xd7;2 line in each of a series of immediately adjacent pixel blocks, prior to scanning a second 2&#xd7;2 line in each of the series of pixel blocks. Each scanned line is then processed for motion compensation in a manner that addresses challenges, including those discussed above, related to buffer size requirements, power consumption requirements and latency.

Motion compensation with subblock scanning

A pixel-data processing circuit adapted to resize pixel data in a first vertically processing mode is reconfigurable to operate in a nonresizing mode, wherein each mode receives pixel data at a first pixel rate and outputs pixel data at a different pixel rate. In one particular example embodiment, pixels are received at two pixels per cycle and output to a storage unit at one pixel per cycle. In a first operational resizing mode, the embodiment includes vertically processing pixel data including polyphase filtering and line-buffering the pixel data, resizing the received pixel data by circulating the data in the line buffers and by filtering the circulated data for the polyphase filtering, and presenting resized pixel data for storage at the first pixel rate. In a second operational nonresizing mode, the pixel data is processed by double-line buffering the pixel data, bypassing the polyphase filtering, and presenting nonresized pixel data for storage at the rate of one pixel per cycle. Using a control circuit, the pixel-data processing circuit can switch between the first operational resizing mode and the second operational nonresizing mode.

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San Jose, CA, United States of America

Shaori Guo