Texas Instruments Corporation

Shaoping Tang

Amitava Chatterjee

Zhiqiang (Jeff) Wu

Imran Khan

Scott Robert Summerfelt

Haowen Bu

Manoj Mehrotra

Freidoon Mehrad

Rajesh B Khamankar

Shashank Sureshchandra Ekbote

Kaiping Liu

Song Zhao

Jong Shik Yoon

Theodore Warren Houston

Seetharaman Sridhar

David Barry Scott

Robert M Wallace

Yi Wei

Alwin J Tsao

James Fred Salzman

Jau-Yuann Yang

Rajni J Aggarwal

Kayvan Sadra

Puneet Kohli

John Mark Anthony

Manuel A Quevedo-Lopez

Youngmin Kim

Shariq Arshad

Chin-yu Tsai

Richard Guerra Roybal

Stan Ashburn

A transistor structure with stress enhancement geometry aligned above the channel region. Also, a transistor structure with stress enhancement geometries located above and aligned with opposite sides of the channel region. Furthermore, methods for fabricating integrated circuits containing transistors with stress enhancement geometries.

Transistor performance modification with stressor structures

An n-channel DEMOS device a pwell finger defining a length and a width direction formed within a doped surface layer. A first nwell is on one side of the pwell finger including a source and a second nwell on an opposite side of the pwell finger includes a drain. A gate stack is over a channel region the pwell finger between the source and drain. A field dielectric layer is on the surface layer defining a first active area including a first active area boundary along the width direction (WD boundary) that has the channel region therein. A first p-type layer is outside the first active area at least a first minimum distance from the WD boundary and a second p-type layer is doped less and is closer to the WD boundary than the first minimum distance.

N-channel demos device

An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

Low cost demos transistor with improved CHC immunity

A method of forming an integrated circuit (IC) includes providing a substrate having a topside semiconductor surface, wherein the topside semiconductor surface includes at least one of N+ buried layer regions and P+ buried layer regions. An epitaxial layer is grown on the topside semiconductor surface. Pwells are formed in the epitaxial layer. Nwells are formed in the epitaxial layer. NMOS devices are formed in and over the pwells, and PMOS devices are formed in and over the nwells.

Radiation hardened integrated circuit

Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning a resist layer overlying a semiconductor substrate to form resist structures about symmetrically located on opposite sides of active regions of the cell, implanting one or more dopant species using a first implant using the resist structures as an implant mask, rotating the semiconductor substrate relative to the first implant by about 180 degrees, and implanting one or more dopant species into the semiconductor substrate with a second implant using the resist structures as an implant mask. A method of performing a symmetric angle implant is also disclosed to provide reduced cross-diffusion within the cell, comprising patterning equally spaced resist structures on opposite sides of the active regions of the cell to equally shadow laterally opposed first and second angled implants.

Intentional pocket shadowing to compensate for the effects of cross-diffusion in SRAMs

Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implantation is commonly used to reduce phosphorus diffusion in the NLDD, but contributes to gated diode leakage (GDL). In high threshold NMOS transistors GDL is commonly a dominant off-state leakage mechanism. This invention provides a method of forming an NMOS transistor in which no carbon is implanted into the NLDD, and the NSD is formed by a pre-amorphizing implant (PAI), a phosphorus implant and a carbon species implant. Use of carbon in the NDS allows a higher concentration of phosphorus, resulting in reduced series resistance and reduced pipe defects. An NMOS transistor with less than 1&#xb7;10cmarsenic in the NSD and a high threshold NMOS transistor formed with the inventive method are also disclosed.

High threshold NMOS source-drain formation with As, P and C to reduce damage

One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body. A source/drain mask is patterned over the semiconductor body implanted source and drain regions are formed that are associated with the gate structure. After forming the implanted source and drain regions, a multi-stage implant is performed on the source and drain regions that comprises at least two implants where the dose and energy of the first implant varies from the dose and energy of the second implant. Other methods and devices are also disclosed.

Multi-stage implant to improve device characteristics

Multiple blanket implantations of one or more p type dopants into a semiconductor substrate are performed to facilitate isolation between nwell regions subsequently formed in the substrate. The blanket implantations are performed through isolation regions in the substrate so that the p type dopants are implanted to depths sufficient to separate the nwell regions. This increased concentration of p type dopants helps to mitigate leakage between the nwell regions as the nwell regions are brought closer together to increase packing densities.

Method of preparing a semiconductor substrate utilizing plural implants under an isolation region to isolate adjacent wells

The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.

Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance

The present invention provides a method () of designing a circuit. The method comprises specifying () a design parameter for memory transistors and logic transistors and selecting () a test retention-mode bias voltage for the memory transistors. The method further comprises determining () a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining () a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used () to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting () the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.

Design method and system for optimum performance in integrated circuits that use power management

A method () of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body () associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking material (). An angled ion implant is performed into the isolation trench () after having the bottom portion thereof filled with the implant masking material, thereby forming a threshold voltage compensation region in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material ().

Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI)

Methods are provided for forming wells in a semiconductor wafer, in which p-wells and n-wells are formed in a substrate, and first p-type dopants are implanted into n-well regions while an n-well mask remains over the wafer to selectively decrease a substrate resistivity in the n-well regions beneath the n-wells. A subsequent blanket implantation provides second p-type dopants into isolation regions of the substrate beneath isolation structures, where the first and second p-type dopants improve well to well isolation without addition of extra masks to the fabrication process.

Methods for improving well to well isolation

The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite-cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.

The present invention employs a no mask, blanket implant of an n-type implant after formation of active regions in NMOS devices. As a result, the implanted n-type dopants counteract portions of strongly p-type HALO or pocket regions creating a smoother dopant profile or transition from a portion of the active regions to the channel. However, the blanket implant is performed at a relatively low energy so as to not significantly alter one or more other portions of the active regions to other portions of the device.

Growing community of inventors

Plano, TX, United States of America

Shaoping Tang