Chinese Academy of Sciences

Beijing Smartlogic Technology Ltd.

Shaolin Xie

Donglin Wang

Tao Wang

Leizu Yin

Jie Hao

Xiaojun Xue

Zhiwei Zhang

Xiao Lin

Zijun Liu

Xing Zhang

Yongyong Yang

An apparatus for parallel filtering, including a multi-granularity memory, a data cache device, a coefficient buffer broadcast device, a vector operation device and a command queue device. The multi-granularity memory is configured to store data to be filtered, filter coefficients and filtering result data. The data cache device is configured to cache, read and update the data to be filtered. The coefficient buffer broadcast device is configured to cache and broadcast the read filter coefficients. The command queue device is configured to store and output a queue of operation commands for the parallel filtering operation. The vector operation device is configured to perform a vector operation based on the data to be filtered and the output coefficient data, and write an operation result into the multi-granularity filtering result storage unit. A method is also provided. The apparatus and method have a fast filtering speed, a smaller number of accesses, an improved usage efficiency, a reduced power consumption and a wide application scope.

Parallel filtering method and corresponding apparatus

A data access method and device for parallel FFT computation. In the method, FFT data and twiddle factors are stored in multi-granularity parallel memories, and divided into groups throughout the computation flow according to a uniform butterfly representation. Each group of data involves multiple butterflies that support parallel computation. Meanwhile, according to the butterfly representation, it is convenient to generate data address and twiddle factor coefficient address for each group. With different R/W granularities, it is possible to read/write data and corresponding twiddle factors in parallel from the multi-granularity memories. The method and device further provide data access devices for parallel FFT computation. In the method and device, no conflict will occur during read/write operations of memories, and no extract step is required for sorting the read/written data. Further, the method and device can flexibly define the parallel granularity according to particular applications.

Data access method and device for parallel FFT computation

A parallel bit reversal device and method. The device includes a parallel bit reversal unit, a butterfly computation and control unit, and a memory. The butterfly computation and control unit is coupled to the memory via a data bus. The parallel bit reversal unit is configured to bit-reverse butterfly group data used by the butterfly computation and control unit. The parallel bit reversal unit includes an address reversing logic coupled to the butterfly computation and control unit, and configured to perform mirror reversal and right-shift operations on a read address from the butterfly computation and control unit.

Parallel bit reversal devices and methods

A method and device for multi-granularity parallel FFT butterfly computation. The method and device read data and twiddle factors for computation in one butterfly group from the input buffers and the twiddle factor buffer at a time, perform multi-stage butterfly computation in parallel using uniform butterfly representations, and write the results back to the input buffers. The method and device greatly reduce the frequency for accessing the memory, improve speed for butterfly computation, and reduce power consumption. The method and device achieve multi-granularity butterfly computation of various data formats in a parallel and efficient manner. The method and device can specify the parallel granularity and data format for butterfly computation according to particular applications, and are applicable to FFT butterfly computation of balanced and unbalanced groups.

Methods and devices for multi-granularity parallel FFT butterfly computation

A multi-granularity parallel FFT computation device including three memories, a butterfly computation device, a state control unit, a data reversing network and a first selector. The three memories are each a multi-granularity parallel memory, and store butterfly group data and twiddle factors corresponding to the butterfly group data. The butterfly computation device perform computations of a butterfly group based on the butterfly group data outputted from the first selector and the corresponding twiddle factors outputted from one of the memories, and write a computation result back to the other two memories. The device can read butterfly group data and corresponding twiddle factors in parallel from the multi-granularity parallel memories with a specific R/W granularity. No memory conflict will occur in the read operation, and no additional process is required for sorting the read/written data.

Multi-granularity parallel FFT computation device

A multi-granularity parallel storage system including a plurality of memories, a shift generator, an address increment lookup unit, an address shifter, a row address generator, and a plurality of address adders. The shift generator is configured to generate a shift value. The address increment lookup unit is configured to generate input data for the address shifter. The address shifter is configured to cyclically shift the input data rightward by Shift elements and then output the shifted data. The row address generator is configured to generate a row address RowAddr and input the generated row address RowAddr to the other input terminal of each address adder. Each address adder is configured to perform a non-sign addition of the input data at the two input terminals to obtain a read/write (R/W) address for one of the memories and input the R/W address to an address input terminal of the memory.

Multi-granularity parallel storage system

A multi-granularity parallel storage system includes an R/W port and a memory. The memory includes W memory blocks and a data gating network. Each of the memory blocks is a 2D array consisting of multiple memory units, and each memory row of the 2D array includes W memory units. For each memory block, one memory row can be read/written at a time, W is the nth power of 2, and n is a natural number.

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Beijing, China

Shaolin Xie