Cambricon Technologies Corporation Limited

Shanghai Cambricon Information Technology Co., Ltd

Chinese Academy of Sciences

Cambricon (xi'an) Semiconductor Co., Ltd.

Beijing Institute of Technology

Guangzhou University

Sanghai Cambricon Information Technology Co., Ltd.

Shaoli Liu

Tianshi Chen

Yunji Chen

Yao Zhang

Bingrui Wang

Shuai Hu

Qi Guo

Xinkai Song

Tian Zhi

Zai Wang

Xiaofu Meng

Jun Liang

Zidong Du

Xiao Lin Zhang

Tao Luo

Jinhua Tao

Shijin Zhang

Dong Han

Xuda Zhou

Daofu Liu

Yimin Zhuang

Zhen Li

Xishan Zhang

Yu Chen

Shengyuan Zhou

Huiying Lan

Yuzhe Luo

Jiaming Guo

Lei Zhang

Cheng Qian

Xiaoyong Zhou

Hongbo Zeng

Yifan Hao

Yongwei Zhao

Guang Jiang

Wei Li

Xiaobing Chen

Yong Yu

Chang Liu

Jianhua Liu

Di Huang

Jie Wei

Xiaoyu Ding

Xiaobin Chen

Zhibin Guo

Hanzhao Zhu

Enhe Liu

Yubin Shen

Jiangtao Ma

Haili Lin

Jiashun Liu

Naijing Lv

Aspects for forward propagation of a convolutional artificial neural network are described herein. The aspects may include a direct memory access unit configured to receive input data from a storage device and a master computation module configured to select one or more portions of the input data based on a predetermined convolution window. Further, the aspects may include one or more slave computation modules respectively configured to convolute a convolution kernel with one of the one or more portions of the input data to generate a slave output value. Further still, the aspects may include an interconnection unit configured to combine the one or more slave output values into one or more intermediate result vectors, wherein the master computation module is further configured to merge the one or more intermediate result vectors into a merged intermediate vector.

Apparatus and methods for forward propagation in convolutional neural networks

Aspects for forward propagation of a multilayer neural network (MNN) in a neural network processor are described herein. As an example, the aspects may include a computation module that includes a master computation module and one or more slave computation modules. The master computation module may be configured to receive one or more groups of MNN data. The one or more groups of MNN data may include input data and one or more weight values and wherein at least a portion of the input data and the weight values are stored as discrete values. The one or more slave computation modules may be configured to calculate one or more groups of slave output values based on a data type of each of the one or more groups of MNN data.

Apparatus and methods for forward propagation in neural networks supporting discrete data

Aspects for neural network operations with fixed-point number of short bit length are described herein. The aspects may include a fixed-point number converter configured to convert one or more first floating-point numbers to one or more first fixed-point numbers in accordance with at least one format. Further, the aspects may include a neural network processor configured to process the first fixed-point numbers to generate one or more process results.

Apparatus and methods for neural network operations supporting fixed point numbers of short bit length

Aspects for backpropagation of a convolutional neural network are described herein. The aspects may include a direct memory access unit configured to receive input data from a storage device and a master computation module configured to select one or more portions of the input data based on a predetermined convolution window. Further, the aspects may include one or more slave computation modules respectively configured to convolute one of the one or more portions of the input data with one of one or more previously calculated first data gradients to generate a kernel gradient, wherein the master computation module is further configured to update a prestored convolution kernel based on the kernel gradient.

Apparatus and methods for training in convolutional neural networks

The application provides a processor and processing method. The processor includes a task segmentation device configured to perform task segmentation according to a task segmentation granularity and a hardware resource division device configured to divide hardware resources of the processor according to a task segmentation result. The processor and processing method provided by the application improve the processing performance and reduce the overhead by performing task segmentation and configuring different hardware according to task segmentation.

Data sharing system and data sharing method therefor

A data processing method includes obtaining content of a descriptor when an operand of a first processing instruction includes the descriptor, where the descriptor is configured to indicate a shape of tensor data and to indicate data address of the tensor data, and executing the first processing instruction according to the content of the descriptor by determining the data address of the tensor data corresponding to the operand of the first processing instruction in a data storage space, according to the content of the descriptor, and according to the data address, executing data processing corresponding to the first processing instruction.

Data processing method and apparatus, and related product for increased efficiency of tensor processing

The present disclosure relates to a learning task compiling method of artificial intelligence processors and related products. The learning task compiling method of artificial intelligence processors includes fusing a redundant neural network layer to a convolution layer, optimizing a structure of a convolution neural network, and compiling a learning task of an artificial intelligence processor based on the optimized convolution neural network. The method may achieve high efficiency for learning task compiling of artificial intelligence processors, and may reduce data exchange during processing when being executed on a device.

Learning task compiling method of artificial intelligence processor and related products

A computing apparatus may be included in a combined processing apparatus. The combined processing apparatus may further include a general interconnection interface and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus may further include a storage apparatus. The storage apparatus is connected to the apparatus and other processing apparatus, respectively. The storage apparatus is used to store data of the apparatus and other processing apparatus. Efficiency of various operations in data processing fields including, for example, an artificial intelligence field can be improved so that overall overheads and costs of the operations can be reduced.

Computing apparatus, integrated circuit chip, board card, electronic device, and computing method

The present disclosure provides a data processing apparatus and related products. The products include a control module including an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store computation instructions associated with an artificial neural network operation; the instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions; and the storage queue unit is configured to store an instruction queue, where the instruction queue includes a plurality of operation instructions or computation instructions to be executed in the sequence of the queue. By adopting the above-mentioned method, the present disclosure can improve the operation efficiency of related products when performing operations of a neural network model.

Data processing apparatus and related products

Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.

Integrated circuit chip apparatus

The present application relates to an operation device and an operation method. The operation device includes a plurality of operation modules. The plurality of operation modules complete an operation of a network model by executing corresponding computational sub-commands in parallel. Each operation module includes at least one operation unit configured to execute a first computational sub-command using first computational sub-data; and a storage unit configured to store the first computational sub-data. The first computational sub-data includes data needed for executing the first computational sub-command. The embodiments of the present application reduces bandwidth requirements for data access and reduces computation and equipment costs.

Parallel processing of network model operations

The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system, and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

Network-on-chip data processing method and device

An integrated circuit chip apparatus and a processing method performed by an integrated circuit chip apparatus are disclosed. The disclosed integrated circuit chip apparatus and processing method are used for executing a multiplication operation, a convolution operation, or a training operation of a neural network. The present technical solution has the advantages of a reduced computational cost and low power consumption.

The application provides an operation method and device. Quantized data is looked up to realize an operation, which simplifies the structure and reduces the computation energy consumption of the data, meanwhile, a plurality of operations are realized.

Processing method and device, operation method and device

Growing community of inventors

Beijing, China

Shaoli Liu