Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Marvell International Limited

Agere Systems Inc.

Avago Technologies International Sales Pte. Limited

Hitachi Global Storage Technologies Netherlands B.v.

Marvellworld Trade Ltd.

Hgst Netherlands, B.v.

Broadcom International Pte. Ltd.

Shaohua Yang

Fan Zhang

Yang Han

Weijun Tan

Zongwang Li

Yuan Xing Lee

Chung-Li Wang

Zining Wu

Haitao Xia

Wu Chang

Changyou Xu

Xuebin Wu

Hongwei Song

Ming Jin

Shu Li

George Mathew

Hao Zhong

Bruce Alexander Wilson

Kiran Kumar Gunnam

Johnson Yen

Richard Rauschmayer

Victor A Krachkovsky

Gregory Burd

Lei Chen

Kelly K Fitzpatrick

Qi Zuo

Yuqing Yang

Anatoli Aleksandrovich Bolotov

Razmik Karabed

Jongseung Park

Jefferson E Singleton

Kapil Gaba

Erich Franz Haratsch

Mikhail I Grinchuk

Jun Xiao

Jin Lu

Xueshi Yang

Nedeljko Varnica

Wei Zhang

Dan Liu

Lav D Ivanovic

Kaitlyn T Nguyen

Yoon Liong Liow

Jun Xu

Panu Chaichanavong

Nenad Miladinovic

Engling Yeo

Henri Sutioso

Dahua Qin

Madhusudan Kalluri

Eugene Pan

Richard Leo Galbraith

Yu Kou

Nitin Nangare

Travis Roger Oenning

Hideki Sawaguchi

Hongxin Song

Seo-How Low

Milos Ivkovic

Ksenija Lakovic

Zhijun Zhao

Han Fang

Rui Cao

Qi Qi

Nils Graef

Eui Seok Hwang

Keke Liu

John Jansen

Harley Burger

Yu Chin Fabian Lim

Ku Hong Jeong

Fuminori Sai

Kenneth M Hall

Mark A Landreth

Ching-Fu Wu

Zhi Kai Chen

Mohammad Shafiul Mobin

Mario Blaum

Avi Steiner

Jeffrey Paul Grundvig

Jingfeng Liu

Yong Wang

Alexander S Podkolzin

Lu Lu

Hakan C Ozdemir

Zhi Bin Li

Xun Zhang

Peter John Windler

Paul G Filseth

Zhiwei Wu

Jianzhong Huang

Xiang Wang

Kaichi Zhang

Suharli Tedja

Bruce Walter McNeill

Sergey Afonin

Joseph Garofalo

Keenan Terrell O'Brien

Yequn Zhang

Douglas M Hamilton

Improved tools and techniques for configuring a write head of a hard disk drive and/or for writing data to a hard disk drive. The write surface of a disk in the hard disk drive can be divided into multiple logical zones, with different interleave sizes for each zone. This scheme can meet latency requirements for regions closer to the center of the write surface while providing for better error rate performance in regions further away from the center of the write surface.

Variable data interleave sizes on hard drives

A semiconductor device, memory system, and method are provided. One example of the semiconductor device is disclosed to include a host interface that enables bi-directional communications with a host computer, a processor subsystem that enables processing of read or write requests received at the host interface, and one or more storage media interfaces, each of the one or more storage media interfaces being convertible between a first configuration and a second configuration, where the first configuration of a storage media interface enables a direct connection with a computer memory device, and where the second configuration of the storage media interface enables a connection with a plurality of computer memory devices via an expander and/or re-timer.

System and method for providing a configurable storage media interface

An apparatus for decoding data includes a data decoding circuit configured to decode data encoded with an irregular low density parity check code based on a parity check matrix with non-uniform column weights, and at least one scaling circuit configured to scale values in the data decoding circuit with a scaling value that is dependent at least in part on a column weight of the likelihood values being scaled.

Irregular low density parity check processing system with non-uniform scaling

The disclosure is directed to a system and method of managing memory resources in a communication channel. According to various embodiments, incoming memory slices associated with a plurality of data sectors are de-interleaved and transferred sequentially through a buffer to a decoder for further processing. To prevent buffer overflow or degraded decoder performance, the memory availability of the buffer is monitored, and transfers are suspended when the memory availability of the buffer is below a threshold buffer availability.

System and method for despreader memory management

Embodiments are related to systems and methods for data transfer, and more particularly to systems and methods for providing transfer margin information.

Systems and methods for accurate transfer margin communication

Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.

Systems and methods for side data based soft data flash memory access

A power regulation system for a read channel of a data storage assembly includes a first voltage regulator for supplying power to the front-end decoder and a second voltage regulator for supplying power to the back-end codec. The second voltage regulator may conserve power reduce supply voltage to the back-end codec when the codec operates at a lower sampling frequency. The second voltage regulator may additionally increase supply voltage to the back-end codec in conjunction with an increase in sampling frequency. The system may additionally include a third voltage regulator for supplying a memory structure of the read channel with only the minimum required operating voltage to prevent leakage power.

Average power saving modes and power architecture for read channel product

Systems and methods for efficient flash memory access

A data processing system is disclosed including a data detector, a data decoder and an alignment detector. The data detector is operable to apply a data detection algorithm to generate detected values for a data sector. The data decoder is operable to apply a data decode algorithm to a decoder input derived from the detected values to yield decoded values. The alignment detector is operable to calculate an offset between multiple versions of the data sector by correlating the multiple versions.

Systems and methods for correlation based data alignment

Systems and methods for efficient soft data based flash memory data recovery

An apparatus for processing data includes a decoder configured to iteratively decode codewords in a data block representing a number of user data sectors, the codewords including user data, folded parity sector data and error correction code parity bits. The folded parity sector data includes a number of parity checks, each with multiple user data bits from each of the data sectors, and with an offset between each of the user data bits from the data sectors determined at least in part by a number of folds in the data sectors. The apparatus also includes a scheduler configured to control decoding of the codewords based at least in part on the folded parity sector data.

Systems and methods for data processing with folded parity sector

Methods and systems are provided for the compression and decompression of data. The compression and decompression of data may include partitioning the data into chunks, analyzing the individual chunks to determine the best compression and decompression encoders to utilize for the next data chunk of a data file. In compressing and decompressing using the mentioned technique, the data is delivered to the requesting client in an efficient and speedy manner.

Semi-dynamic backend coder for data compression

Systems and methods relating generally to data storage, and more particularly to systems and methods for encoding to modify the size of an information set.

Systems and methods for high throughput multi-input compression

Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for multiple codeword processing in a data processing system. An illustrative data processing system includes a processing circuit that processes unprocessed codewords, and provides failed codewords when the processing fails to converge. The system may further include an input buffer circuit that selectively stores a combination of at least one of the unprocessed codewords and at least one of the failed codewords. The input buffer circuit includes a first portion that maintains any of the unprocessed codewords and the failed codewords, and a second portion that maintains only the failed codewords.

Systems and methods for retaining non-converged data sets for additional processing

Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for recovering data where synchronization information is not detected.

Growing community of inventors

San Jose, CA, United States of America

Shaohua Yang