Semiconductor Manufacturing International (shanghai) Corporation

Shanghai Topxgun Robotics Co., Ltd.

Shaobin Li

Yu Zhang

Yun Yang

Liangliang Yin

Lianjie Gao

Shengfen Chiu

Jinshuang Zhang

Lujun Zou

Sheng-Fen Chiu

Shengfin Chiu

An inertial measurement device includes: a shell, sensor components and vibration damping components installed in the shell. The sensor components include an integrated circuit board, an inertial sensor connected to the integrated circuit board, and a barometric sensor connected to the integrated circuit board. The vibration damping components include a first cushion, a first weighting piece, a second weighting piece and a second cushion which are connected successively. An accommodating cavity for accommodating the integrated circuit board is formed between the first weighting piece and the second weighting piece. The first weighting piece includes a holding cavity for accommodating the inertial sensor and a pressure chamber accommodating the barometric sensor and communicating with the exterior of the inertial measurement device.

Inertial measurement device and unmanned aerial vehicle

Provided are a control device for unmanned aerial vehicle and an unmanned aerial vehicle. The control device for unmanned aerial vehicle includes a shell, an inertial measurement device fixed in the shell, a main flight control circuit board electrically connected to the inertial measurement device, and a flexible interface board electrically connected to the main flight control circuit board and appressed against the inwall of the shell. At least one external device is connected to two opposite sides of the flexible interface board through the shell.

Control device for unmanned aerial vehicle and unmanned aerial vehicle

The disclosed subject matter provides a memory device structure and a fabricating method thereof. The memory device structure includes a substrate including a device region and a peripheral region; multiple gate structures; a first dielectric layer, a second barrier layer, multiple source interconnecting lines, and multiple drain region plugs; a second dielectric layer in the device region include multiple source line plugs, and multiple second drain region plugs, and multiple controlling gate plugs; a third dielectric layer including multiple first conductive layers; a fourth dielectric layer including multiple interconnecting structures; a fifth dielectric layer including multiple second conductive layers; and a sixth dielectric layer including multiple third conductive layers.

Memory device structure and fabricating method thereof

A mask may be used in a process for manufacturing a semiconductor device. The semiconductor device may include a source line, a first drain contact terminal, and a second drain contact terminal. The mask may include the following elements: a source-line corresponding light-transmitting portion, which corresponds to the source line; a first-drain-contact-terminal corresponding light-transmitting portion, which corresponds to the first drain contact terminal; a second-drain-contact-terminal corresponding light-transmitting portion, which corresponds to the second drain contact terminal; and a first light-blocking portion, which abuts at least one of the source-line corresponding light-transmitting portion, the first-drain-contact-terminal corresponding light-transmitting portion, and the second-drain-contact-terminal corresponding light-transmitting portion.

Mask and method for manufacturing semiconductor device

A method for manufacturing a semiconductor device may include the following steps: preparing a stacked structure; processing the stacked structure to form a first gate structure and a preliminary structure; forming a dielectric material layer that covers at least the first gate structure; forming a dielectric layer using the dielectric material layer, such that a portion of the dielectric layer is positioned between the first gate structure and the preliminary structure; performing an annealing process on at least one of the dielectric material layer and the dielectric layer; processing the preliminary structure to form a second gate structure; and after the annealing process has been performed, forming a first metal silicide member on the second gate structure and/or forming a second metal silicide member on an active region associated with the second gate structure.

Growing community of inventors

Shanghai, China

Shaobin Li