Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Shao-Yu Wang

Chien-Te Wu

Po Chun Lu

Shang-Chih Hsieh

Nick Tsai

Jun-Jyeh Hsiao

Ming-Chieh Tsai

Jing-Meng Liu

Yun-Han Lee

Chin-Chou Liu

Chien-Hung Lin

Yi-Lin Chuang

Wei-Pin Changchien

Yu-Ting Kuo

Chun-Cheng Ku

Wen-Hsiang Huang

ShengJe Hung

Meng-Hsuan Cheng

Chi-Ta Wu

Henrry Andrian

Yi-Siou Chen

Tai-Lung Chen

Hsiao-Pin Su

An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.

Flip-flop cell

A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.

Low power clock network

A method and system for generating a clock distribution circuit for each macro circuit in an ASIC design are disclosed herein. In some embodiments, a method for generating a clock distribution circuit receives the ASIC design specified in a hardware description language (HDL), places each macro circuit in allocated locations on a semiconductor substrate, generates a custom clock skew information for each macro circuit based on a macro clock delay model, generates a clock distribution circuit for each macro circuit placed on the semiconductor substrate based on the generated custom clock skew information, modifies the clock distribution circuit if the generated clock distribution circuit does not meet timing requirements of the ASIC design, and outputs a physical layout of the ASIC design for manufacturing under a semiconductor fabrication process.

Apparatus and method for advanced macro clock skewing

An accelerator for neural network computing includes hardware engines and a buffer memory. The hardware engines include a convolution engine and at least a second engine. Each hardware engine includes circuitry to perform neural network operations. The buffer memory stores a first input tile and a second input tile of an input feature map. The second input tile overlaps with the first input tile in the buffer memory. The convolution engine is operative to retrieve the first input tile from the buffer memory, perform convolution operations on the first input tile to generate an intermediate tile of an intermediate feature map, and pass the intermediate tile to the second engine via the buffer memory.

Neural network engine with tile-based execution

Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.

Group bounding box region-constrained placement for integrated circuit design

A layout structure and method are described for the layout of chips having libraries of standard cells which minimizes voltage fluctuations on power buses caused by switching circuits in the standard cells. Typically these standard cells are arranged in a row between two power buses. In this invention the standard cells are partitioned into first cells and second cells which can be combined to form the standard cell circuit. The first cells are arranged in a first row and the second cells are arranged in a second row. A first power bus is located above the first row of first cells and a second power bus is located below the second row of second cells. The first power bus and second power bus are electrically connected together. The first power bus supplies a first power supply voltage to the first cells and the second power bus supplies the first power supply voltage to the second cells. A third power bus is located between the first row of first cells and second row of second cells and supplies a second power supply voltage to the first and second cells. The layout can be accomplished automatically using a computer program.

Structure of integrated circuit standard cell library for reducing power supply voltage fluctuation

Antenna diodes used to correct antenna rule violations during the design and formation of integrated circuits are defined within filler cells laid out on the IC chip following the layout of standard electronic module cells and routing of electrical conductors on the chip. The filler cells are disposed in gaps between standard cells containing the electronic modules. The diodes are formed in unconnected pairs that are selectively connected to each other and to an adjacent conductor in order to correct antenna rule violations. Low current leakage is achieved as a result of the use of a fewer number of diode circuits, and the fact that they remain unconnected until used to correct an antenna rule violation.

Low leakage antenna diode insertion for integrated circuits

A conductive interconnection for an integrate circuit between a protected node and a protecting node and its method are disclosed. The conductive interconnection comprises a stacking connector, a routing connector and a top conductive line. The stacking connector is formed to connect the protected node, which is constructed by at least one inner conductive line and at least one conductive plug, alternately. The inner conductive line has a length lower than a threshold value constrained by antenna effect. Moreover, the routing connector, extending toward the stacking connector, is formed to connect the protecting node. The top conductive line is used to connect the stacking connector and the routing connector. Accordingly, the protected node is disconnected from the protecting node prior to the formation of the top conductive line.

Conductive interconnection for semiconductor integrated circuit and method of forming the same

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Hsinchu, Taiwan

Shao-Yu Wang