Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Shao-Yu Li

Huan-Neng Chen

Chang-Fen Hu

Huan-Lung Gu

Chuei-Tang Wang

Kuo-Ji Chen

Bo-Ting Chen

Chia-Wei Hsu

Tsung-Hsin Yu

Ching-Fang Chen

Hao-Chieh Chan

Min-Chuan Wu

Yen-Lin Liu

Hui-Chun Ho

Yeu-Jou Lin

Chi-Wei Chang

Chih-Peng Lin

Jo-Yu Wu

Chien-Hung Zordius Chen

Min-Shueh Yuan

Li-Yu Chen

Tshaw-Chuang Chen

Ta-Chuan Liu

Shao-Te Wu

Wen-Shu Chiang

Wen-Che Liu

Chih-Chung Lo

Wen-Shu Jiaung

In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling 'stair-type' edges to obtain optimized damping waveform.

Driving buffer with configurable slew rate for data transmission

A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a MOS transistor. A first source/drain region of the MOS transistor may be connected to the die-to-die interconnect.

Semiconductor and circuit structures, and related methods

A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Low dropout regulator circuits, input/output device, and methods for operating a low dropout regulator

The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.

Crack detector units and the related semiconductor dies and methods

A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a PMOS transistor and an NMOS transistor. A first source/drain region of the PMOS transistor may be connected to a first source/drain region of the NMOS transistor and the die-to-die interconnect.

A stacked semiconductor arrangement is provided. The stacked semiconductor arrangement includes a dynamic pattern generator layer having an electrical component. The arrangement also includes a monitoring layer configured to evaluate electrical performance of the electrical component.

Electrical component testing in stacked semiconductor arrangement

Devices and methods are provided for monitoring a transient time in a device under test. A circuit includes a transient edge clipper circuit electrically coupled to the device under test. The transient edge clipper circuit is configured to remove voltage levels of a voltage waveform of the device under test which exceed a threshold range to generate a clipped voltage waveform. The circuit also includes logic circuitry electrically coupled to the transient edge clipper circuit. The logic circuitry is configured to generate a time delayed pulse signal representation of the clipped voltage waveform by injecting a predetermined time delay. The circuit also includes a converter circuit electrically coupled to the logic circuitry. The converter circuit is configured to generate a current signal based on the pulse signal representations.

Circuit for monitoring transient time in analog and digital systems

A de-serialization circuit includes a clock generation circuit, a first and a second latch circuit. The clock generation circuit is configured to generate a set of phase clock signals based on a first clock signal and a control signal. Each phase clock signal of the set of phase clock signals being offset from adjacent phase clock signals of the set of phase clock signals by a phase value. The first latch circuit is configured to generate a first set of data signals based on the set of phase clock signals and an input data signal. The second latch circuit is configured to generate a second set of data signals based on a first phase clock signal of the set of phase clock signals and the first set of data signals. Each signal of the second set of data signals being aligned with each other, wherein the first clock signal is non-continuous.

De-serialization circuit and method of operating the same

The present disclosure provides a method for operating a dynamic pattern generator (DPG) having a mirror array. The method comprises receiving a clock signal, determining a time delay based on the period of the clock signal, determining a first clock signal for toggling a first group of mirror cells in the mirror array, determining a second clock signal, lagging behind the first clock signal by the time delay, for toggling a second group of mirror cells in the mirror array, toggling the first group of mirror cells in the mirror array in response to the first clock signal, and toggling the second group of the mirror cells in the mirror array in response to the second clock signal.

Dynamic pattern generator and method of toggling mirror cells of the dynamic pattern generator

A circuit includes a signal generator, a delay pulse generator and a time-to-current converter. The signal generator is configured to generate a first signal including information on a rise delay and a second signal including information on a fall delay. A delay difference exists between the rise delay and the fall delay. The delay pulse generator is configured to provide an additional delay to one of the first and second signals. The time-to-current converter is configured to extract the delay difference.

Circuit and method for delay difference measurement

A method for operating a dynamic pattern generator (DPG) has a mirror array, where an operating clock of the DPG is received and converted to a toggling rate dependent on the operating clock. The toggling rate is compared with a threshold. If the toggling rate is greater than the threshold, the method partitions the mirror array into a plurality of groups. In response to the groups, the method determines a delay value based on the operating clock. The method further generates a delayed clock with the delay with respect to the first clock to the groups of the mirror array.

Frequency dependent clock apparatus and method

In response to a first level of the clock signal, an inverting output of a flip-flop circuit is connected, via a non-inverting input thereof, to a first intermediate node of the flip-flop circuit and a non-inverting output of the flip-flop circuit is connected, via an inverting input thereof, to a second intermediate node of the flip-flop circuit. In response to a second level of the clock signal, the first intermediate node is connected, via a third intermediate node of the flip-flop circuit, to the non-inverting output and the second intermediate node is connected, via a fourth intermediate node of the flip-flop circuit, to the inverting output. A first cross-coupled gates arrangement of the flip-flop circuit is coupled between the first and second intermediate nodes. A second cross-coupled gates arrangement of the flip-flop circuit is coupled between the third and fourth intermediate nodes.

Growing community of inventors

Hsinchu, Taiwan

Shao-Yu Li