Phison Electronics Corporation

Shao-Wei Yen

Yu-Hsiang Lin

Kuo-Hsin Lai

Wei Hung Lin

Cheng-Che Yang

Kuo-Yi Cheng

Tien-Ching Wang

Chih-Kang Yeh

Yu-Cheng Hsu

Yu-Siang Yang

Li-Chun Liang

Siu-Tung Lam

A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: obtaining a data; encoding a plurality of sub-data in the data to obtain a plurality of first error checking and correction codes respectively corresponding to the plurality of sub-data; writing the plurality of sub-data and the plurality of first error checking and correction codes into a first physical programming unit; encoding the plurality of sub-data to obtain a second error checking and correction code; and writing the second error checking and correction code into a second physical programming unit.

Data writing method, memory controlling circuit unit and memory storage device

A decoding method, a memory control circuit unit, and a memory storage device are provided. The method includes: configuring a plurality of read voltage categories, wherein the read voltage categories respectively have a plurality of representative read voltage sets; reading a first physical programming unit according to the representative read voltage sets and executing a decoding operation to obtain a plurality of decoded information; choosing a first read voltage category according to the plurality of decoded information; and reading the first physical programming unit according to the first read voltage sets in the first read voltage category and executing the decoding operation.

Decoding method, memory control circuit unit and memory storage device

A decoding method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the invention. The method includes: reading at least one memory cells by using at least one read voltage level to obtain a codeword; performing a parity check operation on the codeword by an error checking and correcting circuit to generate a syndrome sum corresponding to the codeword; and dynamically adjusting a first parameter used by the error checking and correcting circuit in a first decoding operation based on whether the syndrome sum is less than a first threshold value and performing the first decoding operation on the codeword by the error checking and correcting circuit by using the first parameter.

Decoding method, memory storage device and memory control circuit unit

A decoding method is provided according to an exemplary embodiment of the invention. The decoding method includes: reading a data set from at least two physical units of a rewritable non-volatile memory module by using at least one read voltage level; performing a first-type decoding operation for first data by using the data set and recording decoding information of the first-type decoding operation if the data set conforms to a default condition; adjusting reliability information corresponding to the first data according to the recorded decoding information, and the reliability information is not used in the first-type decoding operation, and the adjusted reliability information is different from default reliability information corresponding to the first data; and performing a second-type decoding operation for the first data according to the adjusted reliability information.

In one exemplary embodiment, the decoding method includes: reading first data from a plurality of first memory cells of a rewritable non-volatile memory module; performing a first decoding operation on the first data based on a first decoding condition; and performing a second decoding operation on the first data based on a second decoding condition if the first decoding operation conforms to a first default status, where a strict level of locating an error bit in the first data based on the second decoding condition is higher than a strict level of locating the error bit in the first data based on the first decoding condition. Therefore, a decoding efficiency of a memory storage device can be improved.

A data processing method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first write data; performing a first stage encoding operation of a low-density parity-check (LDPC) code on the first write data and generating first transition data; performing a second stage encoding operation of the LDPC code on the first transition data and generating a first error correcting code (ECC); receiving second write data; and performing the first stage encoding operation of the LDPC code on the second write data during a time period of performing the second stage encoding operation of the LDPC code on the first transition data. Accordingly, the data processing efficiency corresponding to the LDPC code can be improved.

Data processing method, memory storage device and memory control circuit unit

A decoding method, a memory storage device and a memory control circuit unit. The method includes: reading a plurality of bits from a plurality of first memory cells; performing a first decoding operation on the bits according to first reliability information; and performing a second decoding operation on the bits according to second reliability information if the first decoding operation fails and meets a default condition, and the second reliability information is different from the first reliability information, and a correction ability of the second reliability information for a first type error of the bits is higher than a correction ability of the first reliability information for the first type error. In addition, the first type error is generated by performing a specific programming operation on the first memory cells based on error data.

An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably.

Error processing method, memory storage device and memory controlling circuit unit

A decoding method, a memory storage device and a memory control circuit unit are provided, the decoding method includes: reading a plurality of memory cells according to hard decision voltage to obtain hard bit; performing a parity check procedure for the hard bit to obtain a plurality of syndromes; determining whether the hard bit has error according to the syndromes; if the hard bit has the error, updating the hard bit according to channel information of the hard bit and syndrome weight information corresponding to the hard bit.

A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.

Decoding method, memory storage device and memory controlling circuit unit

A decoding method, a memory storage device and a memory controlling circuit unit are provided. The decoding method includes: reading at least one memory cell according to a first read voltage to obtain at least one first verification bit; executing a hard bit mode decoding procedure according to the first verification bit, and determining whether a first valid codeword is generated by the hard bit mode decoding procedure; if the first valid codeword is not generated by the hard bit mode decoding procedure, obtaining storage information of the memory cell; deciding a voltage number according to the storage information; reading the memory cell according to second read voltages matching the voltage number to obtain second verification bits; and executing a soft bit mode decoding procedure according to the second verification bits. Accordingly, the speed of decoding is increased.

Decoding method, memory storage device, and memory controlling circuit unit

A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: reading memory cells according to a first reading voltage to obtain first verifying bits; executing a decoding procedure including a probability decoding algorithm according to the first verifying bits to obtain first decoded bits, and determining whether a decoding is successful by using the decoded bits; if the decoding is failed, reading the memory cells according to a second reading voltage to obtain second verifying bits, and executing the decoding procedure according to the second verifying bits to obtain second decoded bits. The second reading voltage is different from the first reading voltage, and the number of the second reading voltage is equal to the number of the first reading voltage. Accordingly, the ability for correcting errors is improved.

A decoding method, a memory storage device and a rewritable non-volatile memory module are provided. The method includes: reading a plurality of bits from the rewritable non-volatile memory module according to a reading voltage; performing a parity check of a low density parity check (LDPC) algorithm on the bits to obtain syndromes, and each of the bits is corresponding to at least one of the syndromes; determining whether the bits have an error according to the syndromes; if the bits have the error, obtaining a syndrome weight of each of the bits according to the syndromes corresponding to each of the bits; obtaining an initial value of each of the bits according to the syndrome weight of each of the bits; and performing a first iteration decoding of the LDPC algorithm on the bits according to the initial values. Accordingly, the decoding speed is increased.

Decoding method, memory storage device and rewritable non-volatile memory module

A data reading method for a rewritable non-volatile memory module is provided. The method includes determining a corresponding read voltage based on a critical voltage distribution of memory cells of a word line. The method further includes: if the critical voltage distribution of the memory cells is a right-offset distribution, applying a set of right adjustment read voltage to the word line to read a plurality of bit data as corresponding soft values; and decoding the corresponding soft values to obtain page data stored in the memory cells. Herein, the set of right adjustment read voltage includes a plurality of positive adjustment read voltages and a plurality of negative adjustment read voltages and the number of the positive adjustment read voltages is more than the number of the negative adjustment read voltages. Accordingly, storage states of the memory cells can be identified correctly.

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Kaohsiung, Taiwan

Shao-Wei Yen