United Microelectronics Corp.

Shao-Wei Wang

Yu-Ren Wang

Chien-Liang Lin

Tsuo-Wen Lu

Ying-Wei Yen

Wen-Yi Teng

Chih-Chien Liu

Shih-Hung Tsai

Chin-Cheng Chien

Chih-Wei Yang

Tsun-Min Cheng

Ching-Ling Lin

Min-Chuan Tsai

Po-Jen Chuang

Chia-Ming Kuo

Wei-Hao Huang

Fu-Jung Chuang

Shih-Wei Su

Chih-Chung Chen

Jen-Chieh Lin

Chia-Wei Chang

Yu-Tung Hsiao

Shu-Ming Yeh

Mon-Sen Lin

Kun-Yuan Lo

Pi-Hung Chuang

Chia-Yuan Chang

Pei-Ying Li

Hao Che Feng

Hung Jen Huang

Hsin Min Han

Ping Wei Huang

Ming Shu Chiu

Chien-Ting Lin

Ssu-I Fu

Chun-Hsien Lin

Chih-Wei Chen

Shu-Yen Chan

Kuang-Hsiu Chen

Chun-Wei Yu

Chia-Fu Hsu

Tsai-Yu Wen

Chiu-Hsien Yeh

Chia-Lung Chang

Wen-Tai Chiang

Jei-Ming Chen

Ying-Tsung Chen

Keng-Jen Lin

Yi-Ching Wu

Jian-Cun Ke

Chun-Wei Hsu

I-Ming Lai

Te-Lin Sun

Yi-Hui Lin

Kuan Hsuan Ku

Yu-Min Lin

Kai-Ping Wang

Gin-Chen Huang

Chih-Feng Ku

Tsung-Yu Hou

Wei-Chung Sun

Chao Nan Chen

Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.

Semiconductor structure and manufacturing method thereof

A method of forming a semiconductor device. A substrate having a fin structure is provided. A dummy gate is formed on the fin structure. A polymer block is formed adjacent to a corner between the dummy gate and the fin structure. The polymer block is subjected to a nitrogen plasma treatment, thereby forming a nitridation layer in proximity to a sidewall of the dummy gate under the polymer block. After subjecting the polymer block to the nitrogen plasma treatment, a seal layer is formed on the sidewall of the dummy gate and on the polymer block. An epitaxial layer is then grown on a source/drain region of the fin structure. The dummy gate is then replaced with a metal gate.

Method for forming semiconductor device

The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.

Method for fabricating fin structure for fin field effect transistor

The invention provides a fin structure for a fin field effect transistor, including a substrate. The substrate includes a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view. An isolation layer is disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed. A stress buffer layer is disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins. The stress buffer layer includes a nitride portion.

Fin structure for fin field effect transistor and method for fabrication the same

A semiconductor device includes substrate having a fin structure thereon, a gate structure overlying the fin structure, a polymer block at a corner between the gate structure and the fin structure, and a source/drain region on the fin structure. The polymer block includes a nitridation layer in proximity to a sidewall of the gate structure.

Semiconductor device and fabrication method thereof

The present invention provides a method for forming a stacked layer structure, including: first, a recess is provided, next, an oxide layer is formed in the recess, where the oxide layer has a thickness T, a high-k layer is formed on the oxide layer, a barrier layer is formed on the high-k layer, a silicon layer is then formed on the barrier layer, afterwards, an annealing process is performed on the silicon layer, so as to form an oxygen-containing layer between the silicon layer and the barrier layer, where the oxide layer has a thickness Tafter the annealing process is performed, and satisfies the relationship: (T&#x2212;T)/T&#x2266;0.05, and the silicon layer and the oxygen-containing layer are removed.

Method for forming a stacked layer structure

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

High-K metal gate process for lowering junction leakage and interface traps in NMOS transistor

A semiconductor structure with a multilayer gate oxide is provided. The structure includes a substrate. A multilayer gate oxide is disposed on the substrate, wherein the multilayer gate oxide includes a first gate oxide and a second gate oxide. The first gate oxide contacts the substrate and the second gate oxide is disposed on and contacts the first gate oxide. The second gate oxide is hydrophilic. The first gate oxide is formed by a thermal oxidation process. The second gate oxide is formed by a chemical treatment.

Semiconductor structure with a multilayer gate oxide and method of fabricating the same

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.

Method for fabricating semiconductor device

A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

Metal gate structure and fabrication method thereof

A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer.

Semiconductor process

A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.

Method for processing high-k dielectric layer

A semiconductor process includes the following steps. A substrate is provided. A dielectric layer having a high dielectric constant is formed on the substrate, wherein the steps of forming the dielectric layer include: (a) a metallic oxide layer is formed; (b) an annealing process is performed to the metallic oxide layer; and the steps (a) and (b) are performed repeatedly. Otherwise, the present invention further provides a semiconductor structure formed by said semiconductor process.

Semiconductor structure and fabrication method thereof

A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

Manufacturing method for metal gate using ion implantation

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Taichung, Taiwan

Shao-Wei Wang