Motorola Corporation

Cdc Propriete Intellectuelle

Shao-Wei Pan

Yaron Ben-Arie

Itzhak Barak

Effi Orian

Jacob A Kirschenbaum

Shay-Ping T Wang

Sam M Daniel

Stephen Chih-Hung Ma

Keith Vaclav Warble

Yacov Efrat

Yehuda Shvager

Stephen-Chih-Hung Ma

Dahan Zion

Doron Kolton

Elon Wertheim

Dan Tamir

Shay-Ping Thomas Wang

Sam Mordochai Daniel

An enhanced digital beamformer (EDBF) (210, FIG. 2) is provided for use in a transceiver subsystem (200, FIG. 2) for mitigating interference and increasing the frequency reuse factor in communication systems. The EDBF is used to produce wide nulls (520, FIG. 5) in at least one steerable antenna beam pattern. By directing wide nulls at undesired signals, the EDBF provides a more efficient processing of antenna beam patterns in communication systems. The EDBF is used in geostationary satellites, non-geostationary satellites, and terrestrial communication devices. The EDBF combines a unique algorithm, a special processor, and an array antenna to significantly improve the capacity of current and future communication systems, while remaining compatible with existing modulation techniques.

Method and apparatus for producing wide null antenna patterns

A system (400) alternatively performs real matrix operation in a first mode or performs complex matrix multiplication in a second mode. One input matrix (e.g., {B}) stays in a plurality of memory fields (430-k), while the other input matrix (e.g., {A}) is loaded into a plurality of registers (410-k). Parallel operating groups (405-k, 409-(k+1)) combine elements of {A} with elements of {B}. The groups (405-k, 409-(k+1)) comprise the memory fields (430-k), the registers (410-k) as well as computational units (440-k), switches (420-k) and adder units (460-k). The adder units (460-k) are configured by the switches (420-k) to operate as adders or to operate as accumulators, depending on the mode. Adders provide intermediate results and accumulators accumulate these intermediate results (e.g., Sum) to elements of the resulting matrix {C}. For complex multiplication, real (Re) and imaginary (Im) parts of matrix elements are in processed in adjacent groups. The system (400) uses logarithmic representations of the matrix elements and further comprises a log converter (490) and a plurality of inverse log converters (450-k).

Apparatus and method for matrix multiplication

In a parallel computer system having N parallel computing units a data pipeline connects all the computing units. In addition the computing units are coupled to a random access memory so that each computing unit is assigned to one column of the memory array. To perform a digital signal processing filter operation the required coefficients are stored in the memory so that one or more different filter operations can be carried out in an interleaved way.

Computer system to perform a filter operation using a logarithm and

A parallel processor (110) operates in the LOG domain. A LOG converter (114) receives input data in the NORMAL and converts it to the LOG domain for processing in the parallel processing units PPU-k. Scaling of the input data, is performed in the LOG converter (114) without need for additional multipliers. A constant factor is added to the LOG input data during the LOG conversion process using existing LOG adders already present to perform the LOG conversion. Thus, less total circuitry is needed and the processor can be made more compact, more efficient and less costly.

Method and apparatus for log conversion with scaling

An encoding system (400) receives samples and coefficients from a bus (422). The system comprises a plurality of parallel operating memory devices (430-k), registers (435-k), computing units (440-k), and accumulator units (460-k). The system (400) further comprises a parallel-to-serial buffer (470) coupled to the accumulator units (440-k) and a pair generator (480) for providing amplitude/index pairs. The system (400) performs encoding steps such as transforming, quantizing, zigzagging, rate controlling, and run-length coding. Transforming is explained for the example of a Forward Discrete Cosine Transformation (FDCT). According to a method (500) of the present invention, zigzagging (510) occurs prior to transforming (570) and performed only once when transformation coefficients are provided to the memory devices (430-k) in a zigzag arrangement. Quantizing occurs prior to transforming by pre-calculating the coefficients with quantizers. Pair generator (480) performes rate-controlling and run-length encoding (550). (with reference to FIGS. 2 and 9)

Method and system for encoding

A parallel computer processor that performs L1 norm calculations includes a plurality of processing elements and a data pipeline which couples the processing elements. The data vectors for which the L1 norm is to be calculated are stored in storage lines of a cache memory. In operation each processing element accesses data in its private storage column in the cache memory and calculates a term signal. The term signals are added to form the resulting L1 norm.

Method for calculating an L1 norm and parallel computer processor

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Lake Zurich, IL, United States of America

Shao-Wei Pan