Motorola Corporation

Other

Shao Wei Pan

Shay-Ping T Wang

Nicholas M Labun

Scott Edward Lloyd

Itzhak Barak

Yaron Ben-Arie

Yacov Efrat

Effi Orian

Jacob A Kirschenbaum

Shay Ping Wang

David A Hayner

James Douglas Dworkin

Stephen L Smith

Stephen Chih-Hung Ma

John Michael Buss

Hechun Cai

Frank Fei Zhou

James M Richey

Preferred embodiments of a method and an apparatus for controlling power during a dispatch group call in a wireless communication system are described. A base station ( ) monitors for a transmission from a plurality of mobile stations ( ) via a first communication resource during a time period. The base station ( ) adjusts transmission power associated with a second communication resource based on the transmission from the plurality of mobile stations ( ) via the first communication resource. Further, the base station ( ) determines whether the transmission power associated with the second communication resource is above a transmission power threshold. In response to a failure to receive the transmission from the plurality of mobile stations ( ) via the first communication resource during the time period and a failure to detect the transmission power associated with the second communication resource being above the power threshold, the base station ( ) terminates transmissions to the plurality of mobile stations ( ) via the second communication resource.

Method and apparatus for controlling power during a dispatch group call

A method and system for an IIR filter are provided. A sequence of input signals is converted to a first sequence of log signals, while a sequence of feedback signals is converted to a second sequence of log signals. IIR filtering coefficients are then added to each sequence of log signals to generate a plurality of term signals. The term signals are then converted to inverse-log signals which are summed to produce an output signal. The log/inverse-log conversions of signals are based on estimating a log/inverse-log function using a second-order polynomial.

Method and system for performing an IIR filtering operation

A digital log converter is provided which includes a comparator (10) and a log signal generator (20). Upon receiving a digital input signal (12), the comparator (10) determines whether an upper bit-slice of the input signal (12) equals zero. If the upper bit-slice is zero, the log signal generator (20) subtracts an offset from at least one parameter to generate a log signal (16); otherwise, the log signal generator (20) interpolates the at least one parameter and a lower bit-slice of the input signal (12) to generate the log signal (16).

Log converter utilizing offset and method of use thereof

With reference to FIG. 1 signal processor (10) for performing transformations of sets of input data points comprises a memory for storing a first half input data points and a second half input data points, an adder unit for pairwise adding one real part of each one first half input data point and a second half input data point and providing adder output data, and a computing unit for performing transformations upon the adder output data. Addition for data reduction and data transformation are carried out simultaneously by different units.

Signal processor and method for fast Fourier transformation

A multiply-multiply-accumulate (MMA) system (10) efficiently evaluates matrix products X=F*C. Matrix C is dissected into submatrices A and B taking advantage of symmetry in C. LOG unit (14) converts B, A, and F to LOG values B', A' and F'. These are summed in K parallel calculating units CU's (18) and converted back to Normal domain as P=F*B*A in ALOG units (22) and sent to accumulators ACU's (24). The ACU's (24) accumulate the results. An output buffer (26) combines the results. The B', A' values (32,34) are held in a cache memory (20) and the LOG sums are performed in two steps with intermediate storage.

Apparatus and methods for performing arithimetic operations on vectors

A method and system for an L.sub.1 norm operation are provided. A sequence of input signals is distributed through a data pipeline to a programmable accumulator. The accumulator sums the input signals to generate an output signal. The L.sub.1 norm operation can be performed using the distance between two vectors.

Method and system for performing an L.sub.11 norm operation

Parallel signal processor (10) (FIG. 2) performs a Fourier Transformation of an input signal; The transformation coefficients are converted once to logarithmic form and stored in a cache memory. The input data is converted serially to logarithmic form, and fed to all processing units in parallel. The processing units compute their respective products as additions in the logarithmic domain. Then, the products are converted back to the normal domain. The products with the correct sign are summed by an accumulator of the respective processing element. After the last signal data point has run through the processing elements and the last products are added to their respective sums, all complex output signal data points are complete simultaneously.

Signal processor and method for Fourier Transformation

A converter, which may be used for implementing either logarithmic or inverse-logarithmic functions, includes a memory, a multiplier, and an adder. The memory stores a plurality of parameters which are derived using a least squares method to estimate a logarithmic or inverse-logarithmic function over a domain of input values.

Logarithm/inverse-logarithm converter and method of using same

A method and system for an L.sub.2 norm operation are provided. A sequence of input signals is converted to a sequence of log signals. The sequence of log signals is distributed through a data pipeline to a plurality of processing elements which effectively multiply each log signal by a factor of two to produce a plurality of term signals. The term signals are then converted to inverse-log signals which are summed to produce a feedback signal. The square-root of the feedback signal is computed to generate an output signal. The log/inverse-log conversions of signals are based on estimating a log/inverse-log function using a second-order polynomial. The L.sub.2 norm operation can be performed using the distance between two vectors.

Method and system for performing an L.sub.2 norm operation

The invention relates to a method for electronically representing a number V in a binary data word. Both the exponent and the mantissa are represented as 2' complement. The mantissa is normalized to 0.1.F if the number V is positive where F is the fraction of the mantissa. In case that the number V is negative the fraction F is normalized to 10.F. Usage of this format allows to design an improved adder which requires less hardware.

Method for eletronically representing a number, adder circuit and

A digital beam forming system includes an array of computing units (60-76) for weighting incoming signals and a plurality of summing processors (80-84) for generating output signals that represent weighted sums corresponding to rows within the array. The digital beam forming system can be incorporated in either a transmitter or receiver used in a radio frequency communications system.

Method and system for digital beam forming

A video signal is converted into a coefficient signal for each frame in a video image. Each coefficient signal comprises block coefficient signals which represent the pixels in a pixel map block (420) in a pixel map (410) with the coefficients in a hybrid polynomial. The coefficient signal for only selected frames is transmitted to a receiving computer (130). The coefficient signals are selected based on a number of coefficients in the coefficient signal for a current frame that vary from corresponding coefficients in the coefficient signal for a sequentially previous frame.

Method and system for compressing a video signal using dynamic frame

A pixel map signal is converted into a coefficient signal of block coefficient signals, each representing the pixels in a pixel map block (420) in a pixel map (410) with the coefficients in a hybrid polynomial. The coefficient signal is quantized by dividing each of the coefficient values in each of the block coefficient signals by quantization factors to produce quantized coefficient values which replace the coefficient values. Block coefficient signals which represent an edge block (424) in the pixel map (410) are divided by larger quantization factors than block coefficient signals which represent a center block (422) in the pixel map (410). As a result, smaller quantized coefficient values are obtained so that block coefficient signals which represent an edge block (424) are compressed to a greater extent than block coefficient signals that represent a center block (422) in the pixel map (410).

Method and system for compressing a pixel map signal using dynamic

A computer processor that performs operations in a logarithmic number system (LNS) domain includes a log converter (20) which generates log signals, a data pipeline (22), a plurality of processing elements (231a-f) coupled to respective stages (24a-d) of the data pipeline, an inverse-log converter (28), and a programmable accumulator (232) that performs various summing operations to produce an output signal. An instruction, selected from a set of instructions, is decoded by a control unit (234) to configure the computer processor to perform operations on one or more data streams. Mathematical operations that can be performed by the processor include matrix multiplication, matrix-inversion, fast Fourier transforms (FFT), auto-correlation, cross-correlation, discrete cosine transforms (DCT), polynomial equations, and difference equations in general, such as those used to approximate infinite impulse response (IIR) and finite impulse response (FIR) filters. The computer processor can be used as a co-processor (340) in a general purpose computer system.

Computer processor having a pipelined architecture and method of using

A video signal is converted into a coefficient signal of block coefficient signals for each frame in a video image. Each of the block coefficient signals represents the pixels in a pixel map block (420) with the coefficients in a hybrid polynomial. The hybrid polynomial contains discrete cosine terms, a constant term separated from the discrete cosine terms, and polynomial terms separated from the discrete cosine terms. Coefficient signals for selected frames only are transmitted to a receiving computer (130). The coefficient signals for the selected frames are converted to decompressed pixel map signals and the pixel map signals for unselected frames are interpolated using nonlinear interpolation. The decompressed pixel map signals and interpolated pixel map signals are ordered into an original frame sequence to produce a decompressed video signal.

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Schaumburg, IL, United States of America

Shao Wei Pan