Mediatek Corporation

National Taiwan University

Shao-Wei Feng

Chun-Ming Kuo

Shih-Chi Shen

Yen-Liang Chen

Ang-Sheng Lin

Chi-Hsueh Wang

An-Yeu Wu

Cheng-Zhou Zhan

Tso-Mo Chen

A frequency-generating circuit includes a frequency synthesizer circuit and a controller. The frequency synthesizer circuit generates a radio-frequency clock signal according to a reference clock signal and a channel number. The controller is coupled to the frequency synthesizer circuit, generates a power-down control signal for controlling at least a portion of the frequency synthesizer circuit to power down. The frequency synthesizer circuit includes an accumulator for generating an accumulated value according to the channel number. The frequency synthesizer circuit generates the radio-frequency clock signal according to the reference clock signal and the accumulated value. The controller maintains the accumulated value of the accumulator when the portion of the frequency synthesizer circuit powers down.

Methods for controlling a frequency synthesizer circuit and a frequency-generating circuit utilizing the same

A frequency-generating circuit includes a frequency synthesizer circuit and a reference clock signal processor. The frequency synthesizer circuit receives a processed reference clock signal and generates a radio-frequency clock signal according to the processed reference clock signal. The reference clock signal processor receives an original reference clock signal from an oscillator and processes the original reference clock signal according to an indication signal to generate the processed reference clock signal. The indication signal is generated according to a required reference clock frequency of a communications apparatus. When the required reference clock frequency is high, a frequency of the processed reference clock signal is a multiple of a frequency of the original reference clock signal, and when the required reference clock frequency is low, the frequency of the original reference clock signal is a multiple of the frequency of the processed reference clock signal.

Frequency-generating circuit and communications apparatus

A method for performing channel shortening equalization with frequency notch mitigation is provided, where the method is applied to an electronic device. The method includes: obtaining channel response information from channel estimation to determine a relaxed channel convolution matrix corresponding to the channel response information, with the relaxed channel convolution matrix being a partial matrix of a channel convolution matrix corresponding to the channel response information, wherein the relaxed channel convolution matrix is obtained from omitting a portion of matrix elements of the channel convolution matrix; and based upon the relaxed channel convolution matrix, jointly performing time domain channel shortening control and frequency domain flatness control over the TEQ to perform channel shortening equalization with frequency notch mitigation by utilizing the TEQ. In particular, the portion of matrix elements includes a plurality of rows of matrix elements within the channel convolution matrix. An associated apparatus is also provided.

Method and apparatus for performing channel shortening equalization with frequency notch mitigation

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Taipei, Taiwan

Shao-Wei Feng