Taiwan Semiconductor Manufacturing Comp. Ltd.

Shao-Te Wu

Chia-Jung Chang

Shih-Peng Chang

Shao-Yu Li

A method of operating a power-on (PO) signal generator (which generates a PO signal and includes a supply-variation sensitivity-reducing (SVSR) load coupled between a first reference voltage and a first node, and a first transistor coupled between the first node and a second reference voltage, the SVSR load including a first resistor coupled between the first reference voltage and a second node, and a second transistor coupled between the second node and the first node, each of a control input of the SVSR load and a gate terminal the first transistor being coupled to a monitored voltage) includes: when the monitored voltage rises above a threshold voltage of the first transistor, turning on the first transistor, and pulling first and second voltages correspondingly on the first and second nodes, a third voltage of the second transistor, and the PO signal down to a logical low value.

Method for operating semiconductor device including multi-gated I/O system

A method of generating multiple gating signals for a multi-gated input/output (I/O) system. The system includes an output level shifter and an output driver which are coupled in series between an output node of a core circuit and an external terminal of a corresponding system. The method includes: generating first and second gating signals having corresponding first and second waveforms, the first waveform transitioning from a non-enabling state to an enabling state before the second waveform transitions from the non-enabling state to the enabling state; receiving the first gating signal at the output level shifter; and receiving the second gating signal at the output driver.

Multi-gated I/O system, semiconductor device including and method for generating gating signals for same

A system (for generating multi-gated power-on control signals) includes: a multi-gated input/out (I/O) interface configured to receive at least first and second gating signals; and a gated power-on control (POC) signals generator configured to generate at least the first and second gating signals for the multi-gated I/O interface, a waveform of the first gating signal being different from a waveform of the second gating signal.

Devices and methods are provided for monitoring a transient time in a device under test. A circuit includes a transient edge clipper circuit electrically coupled to the device under test. The transient edge clipper circuit is configured to remove voltage levels of a voltage waveform of the device under test which exceed a threshold range to generate a clipped voltage waveform. The circuit also includes logic circuitry electrically coupled to the transient edge clipper circuit. The logic circuitry is configured to generate a time delayed pulse signal representation of the clipped voltage waveform by injecting a predetermined time delay. The circuit also includes a converter circuit electrically coupled to the logic circuitry. The converter circuit is configured to generate a current signal based on the pulse signal representations.

Growing community of inventors

Hsinchu, Taiwan

Shao-Te Wu