Raydium Semiconductor Corporation

Mediatek Corporation

Raydlum Semiconductor Corporation

Shao-Ping Hung

Cheng-Nan Lin

Shin-Tai Lo

Jun-Ren Shih

Chia-Wei Tai

Chien-Yu Chan

Tien-Yu Lin

Wei-Yeu Chen

Shih Hsun Huang

Tien-Shin Ho

Yuhe Chiou

Huang-Ren Chen

An organic light-emitting diode (OLED) display device and an operating method thereof are disclosed. The OLED display device includes an OLED panel, a non-volatile memory and a volatile memory. The non-volatile memory is coupled to the OLED panel and used for storing accumulated current data from the OLED panel. The volatile memory is coupled between the non-volatile memory and the OLED panel and used for storing a compensation value generated according to the accumulated current data stored in the non-volatile memory. When the OLED panel is directly compensated with the compensation value, the non-volatile memory receives and stores updated accumulated current data of the OLED panel.

Organic light-emitting diode (OLED) display device solving problem of uneven light display

A method for performing polar decoding with aid of notation transformation and associated polar decoder are provided. The method includes: transforming input signals from a 2's complement notation to a signed magnitude notation to generate transformed input signals, wherein during the polar decoding, a plurality of first sub-operations and a plurality of second sub-operations are performed to generate decoding results of the transformed input signals; performing a first sign processing to generate a sign result of a first sub-operation within the plurality of first sub-operations; performing a first magnitude processing to generate a magnitude result of the first sub-operation within the plurality of first sub-operations; performing a second sign processing to generate a sign result of a second sub-operation within the plurality of second sub-operations; and performing a second magnitude processing to generate a magnitude result of the second sub-operation within the plurality of second sub-operations.

Method for performing polar decoding with aid of notation transformation and associated polar decoder

A display driving apparatus including a lightness adjusting unit, a gamma adjusting unit, a pre-charging voltage adjusting unit and a source driving unit is disclosed. The lightness adjusting unit receives and adjusts a lightness of an image data. The gamma adjusting unit adjusts a gamma voltage corresponding to the image data to generate a source data voltage. The pre-charging voltage adjusting unit calculates a highest data voltage and a lowest data voltage which can be outputted by a source electrode and adjusts a pre-charging voltage accordingly to make the adjusted pre-charging voltage the same with the highest data voltage or the lowest data voltage or only a shifted voltage different from the highest data voltage or the lowest data voltage of the image data. The source driving unit outputs the adjusted pre-charging voltage and the source data voltage to a display panel respectively.

Display driving apparatus

A driving circuit and a pin output order arranging method are disclosed. The driving circuit includes (M*N) pins and an arranging module. A first pin&#x2dc;an N-th pin of the (M*N) pins, a (N+1)-th pin&#x2dc;an 2N-th pin of the (M*N) pins, . . . , a [(M&#x2212;1)*N+1]-th pin&#x2dc;a (M*N)-th pin of the (M*N) pins are arranged along a first direction in a specific distance spaced to form a first row of pins&#x2dc;an M-th row of pins. The first row of pins&#x2dc;the M-th row of pins are staggered along a second direction in a staggering way or an aligning way. M and N are integers larger than 1. The arranging module correspondingly arranges the pin output order of the (M*N) pins according to different application modes of the driving circuit.

Driving circuit and pin output order arranging method

A spread spectrum clock signal generator for spreading an input clock signal into an output clock signal includes a clock signal delay chain for delaying the input clock signal into a delay clock signal group having a plurality of delay clock signals, a modulation controller for outputting a counter clock signal control signal, a clock signal selection circuit for selecting, from the delay clock signal group, a modulation clock signal group having a plurality of modulation clock signals, a programmable counter for generating a counting value according to a counter clock signal, and a clock signal output unit for combining the modulation clock signals into the output clock signal according to the counting value, and further generating the counter clock signal, outputted to the programmable counter, according to the counter clock signal control signal.

Spread spectrum clock signal generator

Growing community of inventors

Hsinchu, Taiwan

Shao-Ping Hung