Taiwan Semiconductor Manufacturing Comp. Ltd.

Shao-Lun Chien

Li-Chun Tien

Ting-Wei Chiang

Pin-Dai Sue

Hui-Zhong Zhuang

Ting Yu Chen

Chih-Liang Chen

Po-Chun Wang

Xiangdong Chen

Jerry Chang Jui Kao

Yung-Chen Chien

Tzu-Ying Lin

Seid Hadi Rasouli

An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

Multi-bit structure

A transmission gate structure includes first and second PMOS transistors positioned in a first active area, first and second NMOS transistors positioned in a second active area parallel to the first active area, and four metal segments parallel to the active areas. A first metal segment overlies the first active area, a fourth metal segment overlies the second active area, and second and third metal segments are a total of two metal segments positioned between the first and fourth metal segments. A first conductive path connects gates of the first PMOS and NMOS transistors, a second conductive path connects gates of the second PMOS and NMOS transistors, a third conductive path connects a source/drain (S/D) terminal of each of the first and second PMOS transistors and first and second NMOS transistors and includes a first conductive segment extending across at least three of the four metal segments.

Transmission gate structure

Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

Low hold multi-bit flip-flop

An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.

Tie off device

A method of manufacturing a transmission gate includes overlying a first active area with a first metal zero segment, the first active area including first and second PMOS transistors, overlying a second active area with a second metal zero segment, the second active area including first and second NMOS transistors, and configuring the first and second PMOS transistors and the first and second NMOS transistors as a transmission gate by forming three conductive paths. At least one of the conductive paths includes a first conductive segment perpendicular to the first and second metal zero segments, and the first and second metal zero segments have a first offset distance corresponding to three times a metal zero pitch.

Transmission gate manufacturing method

An integrated circuit disclosed here includes several cell rows extending in a first direction and a multi-bit cell having several bit cells included in the cell rows. The bit cells include M bit cells, and an output signal of a N-th bit cell of the M bit cells is an input signal of a (N+1)-th bit cell of the M bit cells, N and M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell, and the N-th bit cell and the (N+1)-th bit cell are arranged diagonally in different cell rows in the multi-bit cell.

A transmission gate structure includes two PMOS transistors in a first active area, two NMOS transistors in a second active area, a first metal zero segment overlying the first active area, a second metal zero segment offset from the first metal zero segment by a distance, a third metal zero segment offset from the second metal zero segment by the distance, a fourth metal zero segment offset from the third metal zero segment by the distance and overlying the second active area. A first conductive segment overlies a first portion of the first active area included in one or both PMOS transistors, and a second conductive segment overlies a second portion of the second active area included in one or both NMOS transistors. The active areas and metal zero segments are perpendicular to the conductive segments, and the PMOS and NMOS transistors are coupled together through the conductive segments.

Transmission gate structure and method

A transmission gate structure includes first and second PMOS transistors in a first active area and first and second NMOS transistors in a second active area. The first and second PMOS transistors include first and second gate structure, the first NMOS transistor includes a third gate structure coupled to the second gate structure, and the second NMOS transistor includes a fourth gate structure coupled to the first gate structure. A first metal zero segment overlies the first active area, a second metal zero segment is offset from the first metal zero segment by an offset distance, a third metal zero segment is offset from the second metal zero segment by the offset distance, and a fourth metal zero segment is offset from the third metal zero segment by the offset distance and overlies the second active area.

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Hsinchu, Taiwan

Shao-Lun Chien