Taiwan Semiconductor Manufacturing Comp. Ltd.

Shao-Jyun Wu

Sheng-Liang Pan

Huan-Just Lin

Chien-Hao Chen

Hsien-Ming Lee

Chia-Ching Lee

Hung-Chin Chung

Pin-Hsuan Yeh

Hung-Chi Wu

Yung Feng Chang

Ching-Yu Chang

Mei-Yun Wang

Bao-Ru Young

Fu-Kai Yang

Jyu-Horng Shieh

Tung-Heng Hsieh

Chien-Chih Chen

Kuo-Yi Chao

Chao-Hsun Wang

Chen-Yuan Kao

Chia-Wei Chen

Yu-Feng Yin

Shu-Huei Suen

Feng-Yu Chang

Chia-Yang Hung

Jack Kuo-Ping Kuo

Pang-Sheng Chang

Chia-Sheng Chang

A method includes forming first and second semiconductor fins protruding from a substrate. Each of the first and second semiconductor fins includes a stack of alternating channel layers and non-channel layers. The method also includes forming a dielectric helmet between and protruding from the first and the second semiconductor fins, forming a dummy gate stack over the dielectric helmet, patterning the dummy gate stack to expose a portion of the dielectric helmet, removing the exposed portion of the dielectric helmet, and forming a metal gate structure, such that a remaining portion of the dielectric helmet separates the metal gate structure between the first and the second semiconductor fins. The method also includes forming a contact feature over a portion of the metal gate structure. A sidewall of the contact feature is between one of the semiconductor fins and the remaining portion of the dielectric helmet.

Gate isolation features in semiconductor devices and methods of fabricating the same

A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin; forming a first dielectric layer around the first dummy gate structure and around the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure to form a first recess and a second recess in the first dielectric layer, respectively; forming a gate dielectric layer in the first recess and the second recess; forming a first work function layer over the gate dielectric layer in the first and the second recesses; removing the first work function layer from the first recess; converting a surface layer of the first work function layer in the second recess into an oxide; and forming a second work function layer in the first recess over the gate dielectric layer and in the second recess over the oxide.

Fin Field-Effect Transistor device and method

A method for forming a semiconductor device structure includes forming a fin structure with alternating stacked first semiconductor layers and second semiconductor layers over a substrate. The method also includes forming a cladding layer over the fin structure. The method also includes forming a fin isolation structure beside the cladding layer. The method also includes forming a capping layer over the fin isolation structure. The method also includes forming a dummy gate structure across the capping layer. The method also includes patterning the dummy gate structure. The method also includes patterning the capping layer by using the dummy gate structure as a mask layer. The method also includes removing the dummy gate structure.

Semiconductor device structure and method for forming the semiconductor device structure

An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Semiconductor device and method

A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

Tuning threshold voltage through meta stable plasma treatment

Fin field-effect transistor device and method

A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin; forming a first dielectric layer around the first dummy gate structure and around the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure to form a first recess and a second recess in the first dielectric layer, respectively; forming a gate dielectric layer in the first recess and the second recess; forming a first work function layer over the gate dielectric layer in the first recess and in the second recess; removing the first work function layer from the first recess; converting a surface layer of the first work function layer in the second recess into an oxide; and forming a second work function layer in the first recess over the gate dielectric layer and in the second recess over the oxide.

A method includes forming a metal gate structure, wherein the metal gate structure includes a gate dielectric layer and a gate electrode; performing a surface treatment to a top surface of the metal gate structure, wherein the surface treatment converts a top portion of the gate electrode to an oxidation layer; forming a conductive layer above the gate electrode, wherein the forming of the conductive layer includes substituting oxygen in the oxidation layer with a metallic element; and forming a contact feature above the metal gate structure, wherein the contact feature is in direct contact with the conductive layer.

Metal contacts on metal gates and methods thereof

A lithography method is provided in accordance with some embodiments. The lithography method includes forming an under layer of a polymeric material on a substrate; forming a silicon-containing middle layer on the under layer, wherein the silicon-containing middle layer has a silicon concentration in weight percentage less than 20% and is wet strippable; forming a patterned photosensitive layer on the silicon-containing middle layer; performing a first etching process to transfer a pattern of the patterned photosensitive layer to the silicon-containing middle layer; performing a second etching process to transfer the pattern to the under layer; and performing a wet stripping process to the silicon-containing middle layer and the under layer.

Patterning process of a semiconductor structure with a wet strippable middle layer

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Taipei, Taiwan

Shao-Jyun Wu