United Microelectronics Corp.

Untied Microelectronics Corp.

United Microelectorincs Corp.

Shao-Hui Wu

Chi-Fa Ku

Zhibiao Zhou

Chen-Bin Lin

Zhi-Biao Zhou

Yu-Cheng Tung

Chun-Yuan Wu

Su Xing

Ding-Lung Chen

Xiang Li

Tien-Yu Hsieh

Hsiao Yu Chia

Yu-Tse Kuo

Hung-Chan Lin

Chun-Yen Tseng

Chia-Fu Hsu

Ching-Cheng Lung

Yun-Yuan Wang

Shih-Hao Liang

Hai Biao Yao

Pengfei Guo

Yuanli Ding

Ting-Chia Chang

Hai-Biao Yao

An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

Oxide semiconductor device and method of manufacturing the same

The present invention provides a method for forming a semiconductor structure, the method includes: firstly, a substrate having a recess disposed therein is provided, wherein the substrate comprises a silicon substrate, next, a first element is formed in the recess and arranged along a first direction, wherein the first element is made of an oxidation semiconductor material, afterwards, a dielectric layer is formed on the first element, and a second element is formed on dielectric layer and arranged along the first direction, wherein the second element is used as the gate structure of a transistor structure.

Method for forming semiconductor structure

A semiconductor device includes a substrate, a source region and a drain region, a gate dielectric layer, and a ferroelectric material layer. The ferroelectric material layer overlaps with the source region and overlaps with the drain region. The substrate further comprises a channel layer. A gate electrode is disposed on the substrate. The ferroelectric material layer is disposed between the channel layer and the gate electrode.

Semiconductor device having a ferroelectric material layer

A transistor structure includes a first oxide semiconductor layer, a source structure and a drain structure, and a second oxide semiconductor layer. The first oxide semiconductor layer is doped with sulfur. The source structure and the drain structure are disposed on the first oxide semiconductor layer, and a region of the first oxide semiconductor layer between the source structure and the drain structure forms a channel region. The second oxide semiconductor layer doped with sulfur is at least formed on the channel region of the first oxide semiconductor layer.

Transistor structure and method for fabricating the same

A manufacturing method of an oxide semiconductor device includes the following steps. A first oxide semiconductor layer is formed on a substrate. A gate insulation layer is formed on the first oxide semiconductor layer. A first flattening process is performed on a top surface of the first oxide semiconductor layer before the step of forming the gate insulation layer. A roughness of the top surface of the first oxide semiconductor layer after the first flattening process is smaller than the roughness of the top surface of the first oxide semiconductor layer before the first flattening process.

Manufacturing method of oxide semiconductor device

A method of manufacturing an oxide semiconductor transistor is provided in the present invention, which includes the step of providing an oxide semiconductor transistor on the front side of a substrate, attaching a wafer on the front side of the substrate, forming a contact hole extending from the back side of the substrate to the oxide semiconductor layer of the oxide semiconductor transistor, and filling the contact hole with metal material to form a back gate of the oxide semiconductor transistor.

Oxide semiconductor transistor and method of manufacturing the same

A capacitor includes: a bottom electrode; a middle electrode on the bottom electrode; a top electrode on the middle electrode; a first dielectric layer between the bottom electrode and the middle electrode; and a second dielectric layer between the middle electrode and the top electrode. Preferably, the second dielectric layer is disposed on at least a sidewall of the middle electrode to physically contact the first dielectrically, and the middle electrode includes a H-shape.

Capacitor and method for fabricating the same

A control circuit including a first switch to a third switch, an inverter, a first capacitor and a second capacitor. The first switch includes a first terminal receiving a weighting signal, and a second terminal. The second switch includes a first terminal, a control terminal coupled to the second terminal of the first switch, and a second terminal coupled to a reference voltage terminal. The third switch includes a first terminal coupled to the reference voltage terminal, a control terminal, and a second terminal. The inverter includes an input terminal coupled to a data input terminal, and an output terminal. The first capacitor is coupled between the data input terminal and the control terminal of the second switch. The second capacitor is coupled between the output terminal of the inverter and the control terminal of the third switch.

Control circuit for generating linear term of signals

A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared. At least a first dielectric layer is formed on the main surface of the semiconductor substrate. A first OS FET device and a second OS FET device are formed on the first dielectric layer. At least a second dielectric layer is formed to cover the first dielectric layer, the first OS FET device, and the second OS FET device. A first MIM capacitor and a second MIM capacitor are formed on the second dielectric layer. The first MIM capacitor is electrically coupled to the first OS FET device, thereby constituting a DOSRAM cell. The second MIM capacitor is electrically coupled to the second OS FET device, thereby constituting a NOSRAM cell.

Method for fabricating semiconductor memory device having integrated DOSRAM and NOSRAM

A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.

Semiconductor structure

An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, agate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

A method for fabricating capacitor is disclosed. The method includes the steps of: providing a material layer; forming a first conductive layer, a first dielectric layer, and a second conductive layer on the material layer; patterning the first dielectric layer and the second conductive layer to form a patterned first dielectric layer and a middle electrode; forming a second dielectric layer on the first conductive layer and the middle electrode; removing part of the second dielectric layer to form a patterned second dielectric layer; forming a third conductive layer on the first conductive layer and the patterned second dielectric layer, wherein the third conductive layer contacts the first conductive layer directly; and removing part of the third conductive layer to expose part of the patterned second dielectric layer.

Capacitor and fabrication method thereof

The present invention provides a semiconductor memory device, includes at least one static random access memory (SRAM) cell, wherein the SRAM cell includes a first pick-up node, and a dielectric oxide SRAM (DOSRAM), disposed in a first dielectric layer and disposed above the SRAM cell when viewed in a cross section view, wherein the DOSRAM includes an oxide semiconductor filed effect transistor (OSFET) and a capacitor, a source of the OSFET is electrically connected to the first pick-up node of the SRAM cell through a via structure, and at least parts of the first dielectric layer are disposed between the source of the OSFET and the via structure, and the capacitor is disposed above the OSFET and electrically connected to a drain of the OSFET when viewed in the cross section view.

Semiconductor memory device

A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.

Semiconductor transistor device and method for fabricating the same

A semiconductor device includes a main processor, a normally-off processor, and at least one oxide semiconductor random access memory (RAM). The normally-off processor includes at least one oxide semiconductor transistor. The main processor is connected to the normally-off processor, and a clock rate of the main processor is higher than a clock rate of the normally-off processor. The oxide semiconductor RAM is connected to the normally-off processor. An operating method of the semiconductor includes backing up data from the main processor to the normally-off processor and/or the oxide semiconductor RAM.

Growing community of inventors

Singapore, Singapore

Shao-Hui Wu