Taiwan Semiconductor Manufacturing Comp. Ltd.

Shao-huan Wang

Sheng-Hsiung Chen

Kuo-Nan Yang

Wen-Hao Chen

Chun-Chen Chen

Hung-Chih Ou

Chun-Yao Ku

Meng-Xiang Lee

Ren-Zheng Liao

Chung-Hsing Wang

A multi-bit flip-flop includes a first flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The first flip-flop includes a first set pin configured to receive a first set signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second set pin configured to receive the first set signal, and the first set pin and the second set pin are coupled together. The first flip-flop and the second flip-flop are configured to share at least a first clock pin.

Integrated circuit and method of forming same and a system

An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.

Systems and methods for integrated circuit layout

A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability, and includes a first reset pin configured to receive a first reset signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second reset pin configured to receive the first reset signal, and the first reset pin and the second reset pin are coupled together. The first inverter is configured to receive a first clock signal on a first clock pin, and configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.

Growing community of inventors

Hsinchu, Taiwan

Shao-huan Wang