Taiwan Semiconductor Manufacturing Comp. Ltd.

Shao-Chi Yu

Wen-Chuan Tai

Hsiang-Fu Chen

Chia-Ming Hung

Hsin-Ting Huang

Hong-Seng Shue

Tai-I Yang

Allen Timothy Chang

Lien-Yao Tsai

Yuan-Chih Hsieh

Hung-Hua Lin

Ping-Chun Yeh

Bruce C S Chou

Po-Tao Chu

Kun-Ming Huang

Chin-Min Lin

Wei-Ding Wu

Ming-Tai Chung

Shou-Wei Lee

Ping Chun Yeh

A method includes forming a front-end-of-the-line (FEOL) element over a substrate; forming a back-end-of-the-line (BEOL) element over the FEOL element; forming an interconnection structure over the substrate; forming a conductive shielding layer electrically connected to the interconnection structure and vertically overlapping the FEOL element and the BEOL element, wherein the conductive shielding layer is grounded to the substrate through the interconnection structure; and forming a dielectric layer covering the conductive shielding layer.

Device for protecting FEOL element and BEOL element

A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate. an orthogonal projection of the conductive shielding layer on the semiconductor substrate does not overlap with an orthogonal projection of the FEOL element on the semiconductor substrate.

A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.

Semiconductor arrangement and formation thereof

A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.

A method for manufacturing a microelectromechanical systems (MEMS) device is provided. According to some embodiments of the method, a semiconductor structure is provided. The semiconductor structure includes an integrated circuit (IC) substrate, a dielectric layer arranged over the IC substrate, and a MEMS substrate arranged over the IC substrate and the dielectric layer to define a cavity between the MEMS substrate and the IC substrate. The MEMS substrate includes a MEMS hole in fluid communication with the cavity and extending through the MEMS substrate. A sealing layer is formed over or lining the MEMS hole to hermetically seal the cavity with a reference pressure while the semiconductor structure is arranged within a vacuum having the reference pressure. The semiconductor structure resulting from application of the method is also provided.

Method for sealing a cavity of a microelectromechanical systems (MEMS) device using a seal layer covering or lining a hole in fluid communication with the cavity

Device and method for protecting FEOL element and BEOL element

The present disclosure relates to a wafer level chip scale package (WLCSP) with a stress absorbing cap substrate. The cap substrate is bonded to a die through a bond ring and a bond pad arranged on an upper surface of the cap substrate. A through substrate via (TSV) extends from the bond pad, through the cap substrate, to a lower surface of the cap substrate. Further, recesses in the upper surface extend around the bond pad and along sidewalls of the bond ring. The recesses absorb induced stress, thereby mitigating any device offset in the die.

Structure and method to mitigate soldering offset for wafer-level chip scale package (WLCSP) applications

A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.

Semiconductor isolation structure with air gaps in deep trenches

The present disclosure relates to a method of forming a micro-electro mechanical system (MEMs) structure. In some embodiments, the method may be performed by providing a device substrate having a first MEMS device and a second MEMS device, and by providing a capping structure having a first cavity and a second cavity. The capping structure is bonded to the device substrate, such that the first cavity is arranged over the first MEMS device and the second cavity is arranged over the second MEMS device. A first pressure is established within the first cavity and the second cavity. A vent is selectively etched within the capping structure to change the first pressure within the second cavity to a second pressure, which is different from the first pressure.

Microelectromechanical systems (MEMS) devices at different pressures

The present disclosure is directed to a monolithic MEMS (micro-electromechanical system) platform having a temperature sensor, a pressure sensor and a gas sensor, and an associated method of formation. In some embodiments, the MEMS platform includes a semiconductor substrate having one or more transistor devices and a temperature sensor. A dielectric layer is disposed over the semiconductor substrate. A cavity is disposed within an upper surface of the dielectric layer. A MEMS substrate is arranged onto the upper surface of the dielectric layer and has a first section and a second section. A pressure sensor has a first pressure sensor electrode that is vertically separated by the cavity from a second pressure sensor electrode within the first section of a MEMS substrate. A gas sensor has a polymer disposed between a first gas sensor electrode within the second section of a MEMS substrate and a second gas sensor electrode.

Monolithic MEMS platform for integrated pressure, temperature, and gas sensor

The present disclosure relates to a MEMS device with a hermetic sealing structure, and an associated method. In some embodiments, a first die and a second die are bonded at a bond interface region to form a chamber. A conformal thin film structure is disposed covering an outer sidewall of the bond interface region to provide hermetic sealing. In some embodiments, the conformal thin film structure is a continuous thin layer covering an outer surface of the second die and a top surface of the first die. In some other embodiments, the conformal thin film structure comprises several discrete thin film patches disposed longitudinal.

Thin film structure for hermetic sealing

Some embodiments relate to multiple MEMS devices that are integrated together on a single substrate. A device substrate comprising first and second micro-electro mechanical system (MEMS) devices is bonded to a capping structure. The capping structure comprises a first cavity arranged over the first MEMS device and a second cavity arranged over the second MEMS device. The first cavity is filled with a first gas at a first gas pressure. The second cavity is filled with a second gas at a second gas pressure, which is different from the first gas pressure. A recess is arranged within a lower surface of the capping structure. The recess abuts the second cavity. A vent is arranged within the capping structure. The vent extends from a top of the recess to the upper surface of the capping structure. A lid is arranged within the vent and configured to seal the second cavity.

A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.

Growing community of inventors

Hsinchu, Taiwan

Shao-Chi Yu