Silicon Laboratories Inc.

Stmicroelectronics Asia Pacific Pte Limited

Shantonu Bhadury

Kusuma Adi Ningrat

Chee Yu Ng

Giuseppe Noviello

Mudit Srivastava

Hong Lee Koo

Raghavendra Pai Kateel

Hup-Peng Goh

Harikrishnan Prabha Valsala

A memory system including a memory device, cache controller circuitry, and timing circuitry. The memory device has a read enable input for receiving a read enable indication for requesting stored data, and has a minimum delay specification between consecutive read enable indications. The cache controller circuitry provides a read indication during a prefetch mode to read data from a next linear address from the memory device, provides a reading indication while data is being read, and provides a miss indication when a next processor address is not the next linear address. The timing circuitry includes synchronization circuitry receiving the read indication and a clock signal and provides a preliminary read enable indication, read enable circuitry receiving a mask indication and the preliminary read enable indication and providing the read enable indication, and mask circuitry that provides the mask indication when the reading indication and the miss indication are both provided.

System and method of masking memory read request to avoid memory read corruption

Embodiments are disclosed for systems and methods that include pulsing a clock pin of retention cells included within a scan chain to shift a sequence of logic values into the scan chain, so that successive cells are loaded with opposite logic values. Embodiments also include pulsing a retain pin to retain the logic values, and pulsing the clock pin to shift the sequence of logic values through the chain, so that retained logic values are output from, and logic values opposite to the retained logic values are loaded into, the cells. Embodiments also include pulsing a restore pin to restore the retained logic values, pulsing the clock pin to shift the logic values out of the scan chain, comparing the logic values shifted out of the scan chain with the logic values shifted into the scan chain, and detecting a fault on the retain pin based on said comparison.

Method for detecting faults on retention cell pins

A method of matrix sensing using delay-based capacitance sensing, including using X-axis lines as active lines for capacitance measurements and using Y-axis lines as a disturbance to identify the location of a touch in a key matrix is disclosed. A sensing signal is applied to the X-axis lines, and a disturbance signal is applied to the Y-axis lines. If a location is touched, cross-capacitance is reduced, which is measured by sweeping data along the X-axis lines.

Capacitive touch sensor system

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Singapore, Singapore

Shantonu Bhadury