Micron Technology Incorporated

Shantilal Doru

Patrick Robert Khayat

Dung Viet Nguyen

Sivagnanam Parthasarathy

Sampath K Ratnam

Nicholas Julian Richardson

Zhengang Chen

Jun Wan

Steven Michael Kientz

Hope Abigail Henry

Described are systems and methods for memory read calibration based on memory device-originated metrics characterizing voltage distributions. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first metric characterizing threshold voltage distributions of a subset of the plurality of memory cells; determining a first read voltage adjustment; receiving a second metric characterizing the threshold voltage distributions; determining a second read voltage adjustment; and applying the second read voltage adjustment for reading the subset of the plurality of memory cells.

Memory read calibration based on memory device-originated metrics characterizing voltage distributions

Described are systems and methods for memory read threshold tracking based on memory device-originated metrics characterizing voltage distributions. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first value of a metric characterizing threshold voltage distributions of a subset of a set of the plurality of memory cells; determining a first voltage threshold adjustment value; receiving a second value of the metric; determining a second voltage threshold adjustment value; and applying the second voltage threshold adjustment value for reading the set of the plurality of memory cells.

Memory read voltage threshold tracking based on memory device-originated metrics characterizing voltage distributions

In some implementations, a controller of a memory device may obtain a first metric associated with a memory of the memory device using a first memory read configuration. The controller may apply a function to the first metric to obtain a second memory read configuration. The controller may obtain a second metric associated with the memory using the second memory read configuration. The controller may filter the first metric and the second metric to obtain a first filtered metric and a second filtered metric. The controller may provide the first filtered metric and the second filtered metric to a memory management process executing on the controller. The controller may perform an action based on an output of the memory management process, wherein the output is based on the first filtered metric and the second filtered metric.

Filtering metrics associated with memory

A product code decoder to implement a method of bit correction in a codeword buffer to support error correcting code (ECC). The method loads a location entry from a correction queue, where the location entry includes a data word address and bit location information. The method performs a fast path data word address comparison to determine whether data from the data word address is being processed by a previous entry from the correction queue. The method further combines a correction of the data at the data word address specified by the location entry with a correction of a copy of the data being processed based on a previous location entry, in response to a fast path data word address comparison match, and stores the combined data in the codeword buffer.

High throughput bit correction of data inside a word buffer for a product code decoder

A method and system for implementing error correcting code using a product code decoder. The method and system receive a product code, wherein the product code is a matrix of row and column component codes, generate a plurality of row syndromes column syndromes from the received product code, store the plurality of row syndromes in a row syndrome queue, store the plurality of column syndromes in a column syndrome queue, the column and row syndrome queue to support the plurality of modes of operation corresponding to the plurality of phases of decoding the product code, correct the plurality of row syndromes and columns syndromes in the row and column syndrome queues based on errors detected in respective row and column syndromes and errors detecting in overlapping syndromes, and correct the product code in a codeword buffer at locations corresponding to corrections in the plurality of row syndromes and the plurality of column syndromes.

Growing community of inventors

San Diego, CA, United States of America

Shantilal Doru