Commissariat a L'energie Atomique Et Aux Energies Alternatives

Shanthi Sudalaiyandi

Gilles Masson

Mykhailo Zarudniev

Michaël Pelissier

The invention concerns a digital delay locked loop comprising: first and second digitally controllable delay lines (B,B) coupled in series with each other, each comprising a lead portion () and a lag portion (), the first digitally controllable delay line receiving a reference timing signal (TREF) and the second digitally controllable delay line outputting a delayed timing signal (TREF); and a time to digital converter () configured to evaluate a phase difference between the reference signal (TREF) and the delayed timing signal (TREF') and to generate a first control signal (DLEAD_:n]) for controlling said lead portions () or a second control signal (DLAG[:n]) for controlling said lag portions () based on the sign and magnitude of the phase difference.

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Bengaluru, India

Shanthi Sudalaiyandi