Nvidia Corporation

Shantanu Sarangi

Milind Bhaiyyasaheb Sonawane

Amit D Sanghani

Mahmut Yilmaz

Sailendra Chadalavada

Jue Wu

Jonathon E Colburn

Jae Wu

Sailendra Chadalavda

Jonah Matthew Alben

Sachin Satish Idgunji

Rajith Mavila

Venkat Abilash Reddy Nerallapally

Bonita Bhaskaran

Andi Skende

Pavan Kumar Datla Jagannadha

Bala Tarun Nelapatla

Karthikeyan Natarajan

Kaushik Narayanun

Ashish Kumar

Animesh Khare

Rahul Garg

Rajendra Kumar reddyS

Dheepakkumaran Jayaraman

Nithin Anil Valentine

Tezaswi Raja

Ish Chadha

Brian Lawrence Smith

Anubhav Sinha

Gunaseelan Ponnuvel

Anitha Kalva

Hari Unni Krishnan

Sreedhar Narayanaswamy

Suhas Satheesh

Kevin Wilder

Jayesh Kumar Pandey

Hemalkumar Chandrakant Doshi

Sunil Bhavsar

Jaison Daniel Kurien

Purnabha Majumder

Badrinath Srirangam

Charlie Hwang

Kevin Zhou

Adarsh Kalliat Balagopala

Seyed Nima Mozaffari Mojaveri

Kerwin Fu

Milind Sonawane

Chen Fang

Abilash Nerallapally

Kevin Ye

Sumit Raj

Rajendra Kumar ReddyS

Rangavajjula Kameswara Naga Mahesh

Dan Smith

Introduced herein is a technique that reliably measures on-die noise of logic in a chip. The introduced technique places a noise measurement system in partitions of the chip that are expected to cause the most noise. The introduced technique utilizes a continuous free-running clock that feeds functional frequency to the noise measurement circuit throughout the noise measurement scan test. This allows the noise measurement circuit to measure the voltage noise of the logic during a shift phase, which was not possible in the conventional noise measurement method. Also, by being able to measure the voltage noise during a shift phase and hence in both phases of the scan test, the introduced technique can perform a more comprehensive noise measurement not only during ATE testing but as part of IST in the field.

Technique for enabling on-die noise measurement during ate testing and IST

An integrated circuit package includes two or more discrete semiconductor dies coupled to a package substrate. The dies include a primary die and at least one secondary die. The primary die includes an external data transfer interface, a direct memory access ('DMA') controller, a primary cross-die bridge, and at least one primary die-to-die interface. At least one of the secondary dies includes a secondary test controller, a secondary cross-die bridge, and a secondary die-to-die interface. A secondary die is operable to send a test data read request to a host system and to receive a test data read response therefrom. The secondary die is further operable to cause a test to be performed on circuitry within the die responsive to contents in the test data read response.

Test data transfer in multi-die systems

Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.

Asynchronous in-system testing for autonomous systems and applications

In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

Leveraging low power states for fault testing of processing cores at runtime

Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

In system test of chips in functional systems

Techniques for testing semiconductor devices include a semiconductor device having a plurality of components, a test bus, and a test data transfer unit. The test data transfer unit receives, from a host computer, configuration information for performing a test of the semiconductor device, reads, via a high-speed data transfer link, test data associated with the test from memory of the host computer using direct memory access, sends the test data to the plurality of components via the test bus, causes one or more operations to be performed on the semiconductor device to effect at least a portion of the test, and after the one or more operations have completed, retrieves test results of the at least a portion of the test from the test bus and stores, via the high-speed data transfer link, the test results in the memory of the host computer using direct memory access.

Techniques for testing semiconductor devices

Techniques for isolating interfaces while testing a semiconductor device include a semiconductor device having a link interface that couples the semiconductor device to a high-speed data transfer link, a clock control unit that transmits one or more clock signals to the link interface; and a protection module. The protection module asserts a clock stop request to the clock control unit and, in response to receiving a clock stop acknowledgement from the clock control unit, asserts a clamp enable to cause the link interface to be isolated from portions of the semiconductor device. After waiting for a first predetermined period of time to expire, the protection module de-asserts the clock stop request.

Techniques for isolating interfaces while testing semiconductor devices

In-system test of chips in functional systems

During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

Performing testing utilizing staggered clocks

In various examples, one or more components or regions of a processing unit&#x2014;such as a processing core, and/or component thereof&#x2014;may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

The disclosure provides using test processors to provide a more flexible solution compared to the existing DFX blocks that are used for controlling test networks in chips. The test processors provide a highly flexible solution since programming of the test processors can be changed at any time; even after manufacturing, and can support practically an unlimited number of core chips in any configuration. The high flexibility provided via the test processors can reduce engineering effort needed in design and verification, accelerate schedules, and may prevent additional tapeouts in case of DFX design bugs. By making debug and diagnosis easier by providing an opportunity to change debug behavior as needed, the time-to-market timeline can be accelerated. Accordingly, the disclosure provides a chip with a test processor, a multi-chip processing system with a test processor, and a method of designing a chip having a test processor.

Controlling test networks of chips using integrated processors

Latency of in-system test (IST) execution for a hardware component of an in-field (deployed) computing platform may be reduced when a value of a physical operating parameter can be changed without rebooting the computing platform. A test (e.g., patterns or vectors) is executed for varying values of the physical operating parameter (e.g., supply voltage, clock speed, temperature, noise magnitude/duration, operating current, and the like), providing the ability to detect faults in the hardware components.

Hardware-controlled updating of a physical operating parameter for in-field fault detection

Systems and methods enable the updating of tests, test sequences, fault models, and test conditions such as voltage and clock frequencies, over the life cycle of a safety critical application for complex integrated circuits and systems.

On-chip execution of in-system test utilizing a generalized test image

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Saratoga, CA, United States of America

Shantanu Sarangi