California Institute of Technology

Shannon P Jackson

Kevin A Delin

Harold Kirkham

A Sensor Web formed of a number of different sensor pods. Each of the sensor pods include a clock which is synchronized with a master clock so that all of the sensor pods in the Web have a synchronized clock. The synchronization is carried out by first using a coarse synchronization which takes less power, and subsequently carrying out a fine synchronization to make a fine sync of all the pods on the Web. After the synchronization, the pods ping their neighbors to determine which pods are listening and responded, and then only listen during time slots corresponding to those pods which respond.

Sensor web

a Sensor Web formed of a number of different sensor pods. Each of the sensor pods include a clock which is synchronized with a master clock so that all of the sensor pods in the Web have a synchronized clock. The synchronization is carried out by first using a coarse synchronization which takes less power, and subsequently carrying out a fine synchronization to make a fine sync of all the pods on the Web. After the synchronization, the pods ping their neighbors to determine which pods are listening and responded, and then only listen during time slots corresponding to those pods which respond.

A conventional phase-locked loop is improved by replacing its phase detector with one comprising a linear ramp generator and a sample-and-hold circuit, thus eliminating the need for a lowpass loop filter, although the output of the sample-and-hold circuit may be filtered in the case of a very low level modulating signal on the incoming FM signal, but then filtering is not a difficult problem as in a conventional phase-locked loop. The result is FM demodulation by zero-order estimation. For FM demodulation by first-order estimation, the arithmetic difference between adjacent samples is formed, and using a second sample-and-hold circuit an arithmetic difference signal is produced as an input to a second ramp generator that is reset after each sampling cycle to generate a ramp the slope of which is a function of the arithmetic difference signal stored in the second sample-and-hold circuit. The ramp thus generated by the second ramp generator is arithmetically summed with the zero-estimation signal from the first sample-and-hold circuit to form a first-order estimation signal. Filtering such a first-order estimation signal is less of a problem than filtering a zero-order estimation signal.

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Shannon P Jackson